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https://github.com/zephyrproject-rtos/zephyr
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aec9a8c4be
Before introducing the code for ARM64 (AArch64) we need to relocate the current ARM code to a new AArch32 sub-directory. For now we can assume that no code is shared between ARM and ARM64. There are no functional changes. The code is moved to the new location and the file paths are fixed to reflect this change. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H7 CM4 processor
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#if defined(CONFIG_STM32H7_BOOT_CM4_CM7)
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void stm32h7_m4_boot_stop(void)
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{
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/*
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* Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
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* Cortex-M7 to perform system initialization (system clock config,
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* external memory configuration.. )
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*/
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/* Clear pending events if any */
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__SEV();
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__WFE();
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/* Select the domain Power Down DeepSleep */
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LL_PWR_SetRegulModeDS(LL_PWR_REGU_DSMODE_MAIN);
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/* Keep DSTOP mode when D2 domain enters Deepsleep */
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LL_PWR_CPU_SetD2PowerMode(LL_PWR_CPU_MODE_D2STOP);
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LL_PWR_CPU2_SetD2PowerMode(LL_PWR_CPU2_MODE_D2STOP);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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LL_LPM_EnableDeepSleep();
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/* Ensure that all instructions done before entering STOP mode */
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__DSB();
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__ISB();
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/* Request Wait For Event */
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__WFE();
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/* Reset SLEEPDEEP bit of Cortex System Control Register,
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* the following LL API Clear SLEEPDEEP bit of Cortex
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* System Control Register
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*/
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LL_LPM_EnableSleep();
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}
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#endif /* CONFIG_STM32H7_BOOT_CM4_CM7 */
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h7_m4_init(struct device *arg)
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{
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u32_t key;
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key = irq_lock();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/*HW semaphore Clock enable*/
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
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#if defined(CONFIG_STM32H7_BOOT_CM4_CM7)
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/* Activate HSEM notification for Cortex-M4*/
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LL_HSEM_EnableIT_C2IER(HSEM, LL_HSEM_MASK_0);
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/* Boot and enter stop mode */
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stm32h7_m4_boot_stop();
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/* Clear HSEM flag */
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LL_HSEM_ClearFlag_C2ICR(HSEM, LL_HSEM_MASK_0);
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#endif /* CONFIG_STM32H7_BOOT_CM4_CM7 */
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return 0;
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}
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SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0);
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