mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-18 02:01:57 +00:00
5fbf05ce15
On some SoCs the frequency of the system clock is obtained at run time as the exact configuration of the hardware is not known at compile time. On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define directly introduces timing errors. This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call to inline function sys_clock_hw_cycles_per_sec() which always returns correct frequency of the system clock. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
35 lines
957 B
C
35 lines
957 B
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <SEGGER_SYSVIEW.h>
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#include "SEGGER_SYSVIEW_Zephyr.h"
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static void cbSendSystemDesc(void)
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{
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SEGGER_SYSVIEW_SendSysDesc("N=ZephyrSysView");
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SEGGER_SYSVIEW_SendSysDesc("D=" CONFIG_BOARD " "
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CONFIG_SOC_SERIES " " CONFIG_ARCH);
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SEGGER_SYSVIEW_SendSysDesc("O=Zephyr");
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}
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void SEGGER_SYSVIEW_Conf(void)
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{
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SEGGER_SYSVIEW_Init(sys_clock_hw_cycles_per_sec(),
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sys_clock_hw_cycles_per_sec(),
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&SYSVIEW_X_OS_TraceAPI, cbSendSystemDesc);
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#if defined(DT_PHYS_RAM_ADDR) /* x86 */
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SEGGER_SYSVIEW_SetRAMBase(DT_PHYS_RAM_ADDR);
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#elif defined(CONFIG_SRAM_BASE_ADDRESS) /* arm, default */
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SEGGER_SYSVIEW_SetRAMBase(CONFIG_SRAM_BASE_ADDRESS);
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#else
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/* Setting RAMBase is just an optimization: this value is subtracted
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* from all pointers in order to save bandwidth. It's not an error
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* if a platform does not set this value.
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*/
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#endif
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}
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