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https://github.com/zephyrproject-rtos/zephyr
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52e120ed91
The UDOO Neo Full single board computer configuration supports the following hardware features on the Cortex M4 Core: +-----------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | +===========+============+=====================================+ | NVIC | on-chip | nested vector interrupt controller | +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ | GPIO | on-chip | general purpose input/output | +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig Other hardware features are not currently supported by the port. Connections and IOs: The UDOO Neo Full board was tested with the following pinmux controller configuration. +---------------+-----------------+---------------------------+ | Board Name | SoC Name | Usage | +===============+=================+===========================+ | J4 RX | UART5_RX_DATA | UART Console | +---------------+-----------------+---------------------------+ | J4 TX | UART5_TX_DATA | UART Console | +---------------+-----------------+---------------------------+ The board has been tested with the following samples. - samples/hello_world - samples/basic/blinky Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include "device_imx.h"
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static int udoo_neo_full_m4_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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#ifdef CONFIG_GPIO_IMX_PORT_4
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/* GPIO4_IO06 pin mux configuration (red LED) */
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 =
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(5);
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 =
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(6);
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#endif /* CONFIG_GPIO_IMX_PORT_4 */
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#ifdef CONFIG_UART_IMX_UART_5
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/* UART5 pin mux configuration */
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 =
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(2);
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 =
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(2);
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 =
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(6) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_MASK;
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 =
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(6) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_MASK;
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IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT =
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IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(0);
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#endif /* CONFIG_UART_IMX_UART_5 */
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return 0;
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}
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SYS_INIT(udoo_neo_full_m4_init, PRE_KERNEL_1, 0);
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