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74ae6f654e
Add a runner to "flash" and "debug" Cyclone V SoC FPGA Development Kit the runner is based on OpenOCD and GDB Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
42 lines
1.3 KiB
Python
42 lines
1.3 KiB
Python
# Copyright (c) 2018 Foundries.io
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#
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# SPDX-License-Identifier: Apache-2.0
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from runners.core import ZephyrBinaryRunner
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def test_runner_imports():
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# Ensure that all runner modules are imported and returned by
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# get_runners().
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#
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# This is just a basic sanity check against errors introduced by
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# tree-wide refactorings for runners that don't have their own
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# test suites.
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runner_names = set(r.name() for r in ZephyrBinaryRunner.get_runners())
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# Please keep this sorted alphabetically.
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expected = set(('arc-nsim',
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'blackmagicprobe',
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'bossac',
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'canopen',
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'dediprog',
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'dfu-util',
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'esp32',
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'gd32isp',
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'hifive1',
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'intel_cyclonev',
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'intel_s1000',
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'jlink',
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'mdb-nsim',
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'mdb-hw',
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'misc-flasher',
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'nios2',
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'nrfjprog',
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'openocd',
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'pyocd',
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'qemu',
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'spi_burn',
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'stm32cubeprogrammer',
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'stm32flash',
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'xtensa'))
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assert runner_names == expected
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