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https://github.com/zephyrproject-rtos/zephyr
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3f5af00529
The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com> |
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| .. | ||
| 802.15.4 | ||
| clock_control | ||
| console | ||
| pci | ||
| serial | ||
| spi | ||
| ioapic.h | ||
| k6x_mpu.h | ||
| k6x_pmc.h | ||
| k20_mcg.h | ||
| k20_pcr.h | ||
| k20_sim.h | ||
| k20_watchdog.h | ||
| loapic.h | ||
| mvic.h | ||
| rand32.h | ||
| system_timer.h | ||