Jose Alberto Meza 65d93b4ed7 soc: arm: mchp: Allow to configure HW-controlled pins as GPIOs. ... Introduce switch to allow board configuration for VCI pins to remain HW-controled depending on the design. Currently pins are always configured as GPIOs which is not always desirable. Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>		2020-06-10 18:32:57 -04:00
..
arm
atmel_sam
atmel_sam0
bcm_vk	soc: arm: Fix header inclusion from deprecated paths	2020-06-09 10:38:36 +02:00
common/cortex_m
cypress
infineon_xmc
microchip_mec	soc: arm: mchp: Allow to configure HW-controlled pins as GPIOs.	2020-06-10 18:32:57 -04:00
nordic_nrf
nxp_imx
nxp_kinetis	clk: k6x: Enable High Speed RUN (HSRUN) mode for K66F SOC	2020-06-10 13:02:22 -05:00
nxp_lpc
qemu_cortex_a53
silabs_exx32	soc: silabs: Add CPU_HAS_ARM_MPU for all silabs socs	2020-06-09 10:46:47 +02:00
st_stm32	soc: arm: stm32f2 add rtc feature on this serie	2020-06-10 09:40:21 +02:00
ti_lm3s6965
ti_simplelink
xilinx_zynqmp
CMakeLists.txt
Kconfig