Andy Ross ec6a98e5e1 drivers/timer/cavs_timer: Prevent spurious interrupts ... The HDA wall clock timer is a 64 bit timer with 64 bit compare registers, but it's being used from a 32 bit CPU. Writing the comparator piecewise with a 64 bit C assignment will write the low dword first, opening the possibility that the hardware will see time go "backwards" and trigger an interrupt incorrectly. Disable the enable bit while setting the comparator. Found by inspection. In practice this will be very rare, and spurious timer interrupts are supposed to be benign anyway (though they can result in timeout expirations being misaligned to ticks, which might be surprising to applications). Best to get it right. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2020-10-21 06:38:53 -04:00
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altera_avalon_timer_hal.c
apic_timer.c
arcv2_timer0.c
arm_arch_timer.c
cavs_timer.c
cc13x2_cc26x2_rtc_timer.c
CMakeLists.txt
cortex_m_systick.c
hpet.c
Kconfig
Kconfig.stm32_lptim
legacy_api.h
litex_timer.c
loapic_timer.c
mchp_xec_rtos_timer.c
native_posix_timer.c
nrf_rtc_timer.c
riscv_machine_timer.c
rv32m1_lptmr_timer.c
sam0_rtc_timer.c
stm32_lptim_timer.c
sys_clock_init.c
xlnx_psttc_timer_priv.h
xlnx_psttc_timer.c
xtensa_sys_timer.c