mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 08:42:33 +00:00
b1dcf05c68
ARC nSIM simulates all flavors or ARC cores so there's no point in limiting its usage to ARC EM family only. Moreover with upcoming addition of ARC HS family support in Zephyr we'll be re-using nSIM "board" for them as well. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
58 lines
1.5 KiB
XML
58 lines
1.5 KiB
XML
nsim_isa_family=av2em
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nsim_isa_core=3
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arcver=0x43
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nsim_isa_rgf_num_banks=1
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nsim_isa_rgf_num_regs=32
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nsim_isa_rgf_num_wr_ports=1
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nsim_isa_big_endian=0
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nsim_isa_lpc_size=32
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nsim_isa_pc_size=32
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nsim_isa_addr_size=32
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nsim_isa_code_density_option=2
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nsim_isa_div_rem_option=1
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nsim_isa_turbo_boost=1
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nsim_isa_swap_option=1
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nsim_isa_bitscan_option=1
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nsim_isa_mpy_option=8
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nsim_isa_shift_option=3
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nsim_isa_dsp_option=2
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nsim_isa_dsp_complex_option=1
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nsim_isa_dsp_divsqrt_option=1
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nsim_isa_dsp_accshift_option=1
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nsim_isa_enable_timer_0=1
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nsim_isa_timer_0_int_level=1
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nsim_isa_enable_timer_1=1
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nsim_isa_timer_1_int_level=0
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nsim_isa_enable_sec_timer_0=1
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nsim_isa_stimer_0_int_level=1
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nsim_isa_num_actionpoints=2
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nsim_isa_stack_checking=1
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nsim_isa_smart_stack_entries=8
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mpu_sid_option=1
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mpu_regions=16
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mpu_version=4
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nsim_isa_number_of_interrupts=22
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nsim_isa_number_of_levels=4
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nsim_isa_number_of_external_interrupts=17
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nsim_isa_intvbase_preset=0x0
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nsim_isa_intvbase_preset_s=0x0
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dcache=16384,32,2,a
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nsim_isa_dc_feature_level=2
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icache=16384,32,2,a
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nsim_isa_ic_feature_level=2
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dccm_size=0x80000
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dccm_base=0x80000000
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nsim_isa_dccm_interleave=1
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iccm0_size=0x80000
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iccm0_base=0x00000000
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nsim_isa_has_secure=1
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nsim_isa_sec_modes_option=1
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iccm0_sec_lvl=NS
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dccm_sec_lvl=NS
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nsim_isa_pct_counters=8
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nsim_isa_dmac_option=1
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nsim_isa_dmac_channels=2
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nsim_isa_dmac_registers=0
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nsim_isa_dmac_fifo_depth=2
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nsim_isa_dmac_int_config=single_internal
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nsim_mem-dev=uart0,base=0xf0000000,irq=24 |