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https://github.com/zephyrproject-rtos/zephyr
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ccb4b1ec47
It is desired to have the peripheral writes completed to clear the interrupt condition and de-assert the interrupt request to GIC before EOI write. Failing which spurious interrupt will occur. A barrier is needed to ensure peripheral register write transfers are complete before EOI is done. GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point of view. However these writes may pass over different interconnects, bridges, buffers leaving some rare chances for the actual write to complete out of order. GICv3 ICC EOI system register writes have no ordering against nGnR(n)E memory writes as they are over different interfaces. Hence a dsb can ensure from core no writes are issued before the previous writes are *complete*. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> |
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| .. | ||
| adc | ||
| audio | ||
| bluetooth | ||
| can | ||
| clock_control | ||
| console | ||
| counter | ||
| crypto | ||
| dac | ||
| debug | ||
| display | ||
| dma | ||
| eeprom | ||
| entropy | ||
| espi | ||
| ethernet | ||
| flash | ||
| gpio | ||
| hwinfo | ||
| i2c | ||
| i2s | ||
| ieee802154 | ||
| interrupt_controller | ||
| ipm | ||
| kscan | ||
| led | ||
| led_strip | ||
| lora | ||
| modem | ||
| net | ||
| neural_net | ||
| pcie | ||
| peci | ||
| pinmux | ||
| ps2 | ||
| ptp_clock | ||
| pwm | ||
| sensor | ||
| serial | ||
| spi | ||
| timer | ||
| usb | ||
| video | ||
| watchdog | ||
| wifi | ||
| CMakeLists.txt | ||
| Kconfig | ||