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https://github.com/zephyrproject-rtos/zephyr
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We re-wrote the xtensa arch code, but never got around to purging the old implementation. Removed those boards which hadn't been moved to the new arch code. These were all xt-sim simulator targets and not real hardware. Fixes: #18138 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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.. | ||
altera_avalon_timer_hal.c | ||
apic_timer.c | ||
arcv2_timer0.c | ||
CMakeLists.txt | ||
cortex_m_systick.c | ||
hpet.c | ||
Kconfig | ||
legacy_api.h | ||
litex_timer.c | ||
loapic_timer.c | ||
mchp_xec_rtos_timer.c | ||
native_posix_timer.c | ||
nrf_rtc_timer.c | ||
riscv_machine_timer.c | ||
rv32m1_lptmr_timer.c | ||
sam0_rtc_timer.c | ||
sys_clock_init.c | ||
xlnx_psttc_timer.c | ||
xtensa_sys_timer.c |