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https://github.com/zephyrproject-rtos/zephyr
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3ae52624ff
Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
47 lines
1.1 KiB
Plaintext
47 lines
1.1 KiB
Plaintext
# SPDX-License-Identifier: Apache-2.0
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# Zephyr Kernel Configuration
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CONFIG_ARM=y
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CONFIG_SOC_SERIES_STM32F1X=y
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# Platform Configuration
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CONFIG_SOC_STM32F107XC=y
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CONFIG_BOARD_STM3210C_EVAL=y
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# General Kernel Options
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CONFIG_CORTEX_M_SYSTICK=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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# enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Pinmux Driver
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CONFIG_PINMUX=y
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# GPIO Controller
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CONFIG_GPIO=y
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# RCC configuration
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CONFIG_CLOCK_CONTROL=y
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# Clock configuration for Cube Clock control driver
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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CONFIG_CLOCK_STM32_PLL_SRC_PLL2=n
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# however, the board does not have an external oscillator, so just use
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_PREDIV1=1
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not to exceed 36MHz limit
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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