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https://github.com/zephyrproject-rtos/zephyr
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375b7171b4
After introducing STM32Cube based clock control driver for stm32 family, update GPIO driver to support it. Once supported across the whole family, we clean up will be done. Change-Id: If50cb580cb01dc1d38557e54f19a8260feaa504e Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32_GPIO_H_
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#define _STM32_GPIO_H_
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/**
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* @file header for STM32 GPIO
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*/
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#include <clock_control/stm32_clock_control.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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#include <gpio.h>
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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/* GPIO buses definitions */
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#ifdef CONFIG_SOC_SERIES_STM32F3X
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#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
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#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
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#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
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#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
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#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
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#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
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#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
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#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
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#elif CONFIG_SOC_SERIES_STM32L4X
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#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
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#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
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#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
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#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
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#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
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#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
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#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
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#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
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#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
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#endif /* CONFIG_SOC_SERIES_.. */
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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/**
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* @brief configuration of GPIO device
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*/
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struct gpio_stm32_config {
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/* port base address */
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uint32_t *base;
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/* IO port */
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enum stm32_pin_port port;
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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struct stm32_pclken pclken;
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#elif CONFIG_SOC_SERIES_STM32F4X
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struct stm32f4x_pclken pclken;
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#else /* SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X */
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/* clock subsystem */
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clock_control_subsys_t clock_subsys;
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#endif
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};
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/**
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* @brief driver data
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*/
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struct gpio_stm32_data {
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/* Enabled INT pins generating a cb */
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uint32_t cb_pins;
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/* user ISR cb */
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sys_slist_t cb;
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};
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/**
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* @brief helper for mapping of GPIO flags to SoC specific config
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*
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* @param flags GPIO encoded flags
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* @param out conf SoC specific pin config
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*
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* @return 0 if flags were mapped to SoC pin config
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*/
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int stm32_gpio_flags_to_conf(int flags, int *conf);
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/**
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* @brief helper for configuration of GPIO pin
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*
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* @param base_addr GPIO port base address
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* @param pin IO pin
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* @param func GPIO mode
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* @param altf Alternate function
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*/
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int stm32_gpio_configure(uint32_t *base_addr, int pin, int func, int altf);
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/**
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* @brief helper for setting of GPIO pin output
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*
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* @param base_addr GPIO port base address
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* @param pin IO pin
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* @param value 1, 0
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*/
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int stm32_gpio_set(uint32_t *base, int pin, int value);
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/**
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* @brief helper for reading of GPIO pin value
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*
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* @param base_addr GPIO port base address
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* @param pin IO pin
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* @return pin value
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*/
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int stm32_gpio_get(uint32_t *base, int pin);
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/**
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* @brief enable interrupt source for GPIO pin
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* @param port
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* @param pin
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*/
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int stm32_gpio_enable_int(int port, int pin);
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#endif /* _STM32_GPIO_H_ */
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