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https://github.com/zephyrproject-rtos/zephyr
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75d23d5916
This commit adds support for multiple hardware TX and RX queues. The number of the queues to use can be configured through defconfig. Packets are sent and received through different hardware queues depending on their priority. Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
171 lines
4.2 KiB
Plaintext
171 lines
4.2 KiB
Plaintext
# Kconfig - Atmel SAM Ethernet (GMAC) driver configuration options
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#
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# Copyright (c) 2016 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig ETH_SAM_GMAC
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bool
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prompt "Atmel SAM Ethernet driver"
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depends on SOC_FAMILY_SAM
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help
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Enable Atmel SAM MCU Family Ethernet driver.
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if ETH_SAM_GMAC
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config ETH_SAM_GMAC_NAME
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string "Device name"
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default "ETH_0"
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help
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Device name allows user to obtain a handle to the device object
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required by all driver API functions. Device name has to be unique.
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config ETH_SAM_GMAC_QUEUES
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int "Number of hardware TX and RX queues"
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default 1
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range 1 3
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help
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Select the number of hardware queues used by the driver. Packets will be
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routed to appropriate queues based on their priority.
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config ETH_SAM_GMAC_TX_TIMEOUT_MSEC
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int "TX timeout"
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default 5000
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range 1000 10000
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help
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The maximum time in msec that the driver will wait for a TX interrupt
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after scheduling a packet to be sent. If no interrupt is reported during
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that period, all TX packets in the queue will be discarded.
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config ETH_SAM_GMAC_BUF_RX_COUNT
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int "Network RX buffers preallocated by the SAM ETH driver"
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default 18
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help
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Number of network buffers that will be permanently allocated by the
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Ethernet driver. These buffers are used in receive path. They are
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preallocated by the driver and made available to the GMAC module to be
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filled in with incoming data. Their number has to be large enough to fit
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at least one complete Ethernet frame. SAM ETH driver will always allocate
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that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT
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which is a total amount of RX data buffers used by the whole networking
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stack. One has to ensure that NET_PKT_RX_COUNT is large enough to
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fit at least two Ethernet frames: one being received by the GMAC module
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and the other being processed by the higher layer networking stack.
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config ETH_SAM_GMAC_IRQ_PRI
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int "Interrupt priority"
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default 0
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help
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IRQ priority of Ethernet device
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choice ETH_SAM_GMAC_MAC_SELECT
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prompt "MAC address"
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help
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Choose how to configure MAC address.
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config ETH_SAM_GMAC_MAC_MANUAL
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bool "Manual"
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help
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Assign an arbitrary MAC address.
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config ETH_SAM_GMAC_MAC_I2C_EEPROM
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bool "Read from an I2C EEPROM"
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help
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Read MAC address from an I2C EEPROM.
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endchoice
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if ETH_SAM_GMAC_MAC_MANUAL
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config ETH_SAM_GMAC_MAC0
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hex "MAC Address Byte 0"
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default 0
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range 0 0xff
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config ETH_SAM_GMAC_MAC1
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hex "MAC Address Byte 1"
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default 0
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range 0 0xff
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config ETH_SAM_GMAC_MAC2
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hex "MAC Address Byte 2"
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default 0
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range 0 0xff
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config ETH_SAM_GMAC_MAC3
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hex "MAC Address Byte 3"
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default 0
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range 0 0xff
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config ETH_SAM_GMAC_MAC4
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hex "MAC Address Byte 4"
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default 0
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range 0 0xff
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config ETH_SAM_GMAC_MAC5
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hex "MAC Address Byte 5"
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default 0
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range 0 0xff
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endif # ETH_SAM_GMAC_MAC_MANUAL
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if ETH_SAM_GMAC_MAC_I2C_EEPROM
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config ETH_SAM_GMAC_MAC_I2C_SLAVE_ADDRESS
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hex "I2C 7-bit EEPROM chip address"
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range 0 0xff
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help
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I2C 7-bit address of the EEPROM chip.
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config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS
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hex "I2C EEPROM internal address"
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range 0 0xffffffff
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help
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Internal address of the EEPROM chip where the MAC address is stored.
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Chips with 1 to 4 byte internal address size are supported. Address
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size has to be configured in a separate Kconfig option.
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config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE
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int "I2C EEPROM internal address size"
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default 1
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range 1 4
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help
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Size (in bytes) of the internal EEPROM address.
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config ETH_SAM_GMAC_MAC_I2C_DEV_NAME
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string "I2C bus driver device name"
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help
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Device name, e.g. I2C_0, of an I2C bus driver device. It is required to
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obtain handle to the I2C device object.
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endif # ETH_SAM_GMAC_MAC_I2C_EEPROM
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choice
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prompt "MII/RMII Interface to the Physical Layer"
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config ETH_SAM_GMAC_RMII
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bool "RMII"
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config ETH_SAM_GMAC_MII
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bool "MII"
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endchoice
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config ETH_SAM_GMAC_PHY_ADDR
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int "GMAC PHY Address"
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default 0
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help
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GMAC PHY Address as used by IEEE 802.3, Section 2 MII compatible PHY
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transceivers. If you have a single PHY on board it is safe to leave it
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at 0 which is the broadcast address.
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config PTP_CLOCK_SAM_GMAC
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bool "SAM GMAC PTP clock driver support"
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default n
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default y if NET_GPTP
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select PTP_CLOCK
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depends on NET_GPTP
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help
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Enable SAM GMAC PTP Clock support.
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endif # ETH_SAM_GMAC
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