mirror of
https://github.com/zephyrproject-rtos/zephyr
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3842c60ce3
Add the clock driver for the STM32L4 series. Change-Id: Icdf79061f163d8d00187b382d1564422fb875c5b Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
394 lines
9.9 KiB
C
394 lines
9.9 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 BayLibre, SAS
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Driver for Reset & Clock Control of STM32F10x family processor.
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*
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* Based on reference manual:
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* STM32L4x1, STM32L4x2, STM32L431xx STM32L443xx STM32L433xx, STM32L4x5,
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* STM32l4x6
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 7: Low-, medium-, high- and XL-density reset and
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* clock control
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*/
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#include <soc.h>
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#include <errno.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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struct stm32l4x_rcc_data {
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uint8_t *base;
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};
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static inline int stm32l4x_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32l4x_rcc_data *data = dev->driver_data;
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volatile struct stm32l4x_rcc *rcc = (struct stm32l4x_rcc *)(data->base);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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uint32_t base = STM32L4X_CLOCK_BASE(subsys);
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uint32_t bit = 1 << STM32L4X_CLOCK_BIT(subsys);
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switch (base) {
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case STM32L4X_CLOCK_AHB1_BASE:
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rcc->ahb1enr |= bit;
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break;
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case STM32L4X_CLOCK_AHB2_BASE:
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rcc->ahb2enr |= bit;
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break;
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case STM32L4X_CLOCK_AHB3_BASE:
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rcc->ahb3enr |= bit;
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break;
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case STM32L4X_CLOCK_APB1_1_BASE:
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rcc->apb1enr1 |= bit;
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break;
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case STM32L4X_CLOCK_APB1_2_BASE:
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rcc->apb1enr2 |= bit;
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break;
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case STM32L4X_CLOCK_APB2_BASE:
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rcc->apb2enr |= bit;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static inline int stm32l4x_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32l4x_rcc_data *data = dev->driver_data;
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volatile struct stm32l4x_rcc *rcc =
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(struct stm32l4x_rcc *)(data->base);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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uint32_t base = STM32L4X_CLOCK_BASE(subsys);
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uint32_t bit = 1 << STM32L4X_CLOCK_BIT(subsys);
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switch (base) {
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case STM32L4X_CLOCK_AHB1_BASE:
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rcc->ahb1enr &= bit;
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break;
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case STM32L4X_CLOCK_AHB2_BASE:
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rcc->ahb2enr &= bit;
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break;
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case STM32L4X_CLOCK_AHB3_BASE:
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rcc->ahb3enr &= bit;
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break;
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case STM32L4X_CLOCK_APB1_1_BASE:
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rcc->apb1enr1 &= bit;
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break;
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case STM32L4X_CLOCK_APB1_2_BASE:
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rcc->apb1enr2 &= bit;
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break;
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case STM32L4X_CLOCK_APB2_BASE:
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rcc->apb2enr &= bit;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/**
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* @brief helper for mapping a setting to register value
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*/
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struct regval_map {
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int val;
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int reg;
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};
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static int map_reg_val(const struct regval_map *map, size_t cnt, int val)
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{
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size_t i;
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for (i = 0; i < cnt; i++) {
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if (map[i].val == val) {
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return map[i].reg;
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}
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}
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return 0;
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}
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/**
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* @brief map APB prescaler setting to register value
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*/
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static int apb_prescaler(int prescaler)
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{
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if (prescaler == 0) {
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return STM32L4X_RCC_CFG_HCLK_DIV_0;
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}
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const struct regval_map map[] = {
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{0, STM32L4X_RCC_CFG_HCLK_DIV_0},
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{2, STM32L4X_RCC_CFG_HCLK_DIV_2},
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{4, STM32L4X_RCC_CFG_HCLK_DIV_4},
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{8, STM32L4X_RCC_CFG_HCLK_DIV_8},
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{16, STM32L4X_RCC_CFG_HCLK_DIV_16},
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};
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return map_reg_val(map, ARRAY_SIZE(map), prescaler);
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}
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/**
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* @brief map AHB prescaler setting to register value
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*/
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static int ahb_prescaler(int prescaler)
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{
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if (prescaler == 0)
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return STM32L4X_RCC_CFG_SYSCLK_DIV_0;
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const struct regval_map map[] = {
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{0, STM32L4X_RCC_CFG_SYSCLK_DIV_0},
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{2, STM32L4X_RCC_CFG_SYSCLK_DIV_2},
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{4, STM32L4X_RCC_CFG_SYSCLK_DIV_4},
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{8, STM32L4X_RCC_CFG_SYSCLK_DIV_8},
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{16, STM32L4X_RCC_CFG_SYSCLK_DIV_16},
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{64, STM32L4X_RCC_CFG_SYSCLK_DIV_64},
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{128, STM32L4X_RCC_CFG_SYSCLK_DIV_128},
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{256, STM32L4X_RCC_CFG_SYSCLK_DIV_256},
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{512, STM32L4X_RCC_CFG_SYSCLK_DIV_512},
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};
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return map_reg_val(map, ARRAY_SIZE(map), prescaler);
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}
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static uint32_t get_ahb_clock(uint32_t sysclk)
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{
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/* AHB clock is generated based on SYSCLK */
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uint32_t sysclk_div = CONFIG_CLOCK_STM32L4X_AHB_PRESCALER;
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if (sysclk_div == 0) {
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sysclk_div = 1;
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}
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return sysclk / sysclk_div;
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}
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static uint32_t get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
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{
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if (prescaler == 0) {
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prescaler = 1;
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}
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return ahb_clock / prescaler;
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}
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static
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int stm32l4x_clock_control_get_subsys_rate(struct device *clock,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(clock);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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uint32_t base = STM32L4X_CLOCK_BASE(subsys);
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/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
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uint32_t ahb_clock =
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get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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switch (base) {
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case STM32L4X_CLOCK_AHB1_BASE:
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case STM32L4X_CLOCK_AHB2_BASE:
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case STM32L4X_CLOCK_AHB3_BASE:
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*rate = ahb_clock;
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break;
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case STM32L4X_CLOCK_APB1_1_BASE:
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case STM32L4X_CLOCK_APB1_2_BASE:
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*rate = get_apb_clock(ahb_clock,
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CONFIG_CLOCK_STM32L4X_APB1_PRESCALER);
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break;
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case STM32L4X_CLOCK_APB2_BASE:
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*rate = get_apb_clock(ahb_clock,
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CONFIG_CLOCK_STM32L4X_APB2_PRESCALER);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct clock_control_driver_api stm32l4x_clock_control_api = {
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.on = stm32l4x_clock_control_on,
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.off = stm32l4x_clock_control_off,
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.get_rate = stm32l4x_clock_control_get_subsys_rate,
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};
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/**
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* @brief setup embedded flash controller
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*
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* Configure flash access time latency depending on SYSCLK.
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*/
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static inline void setup_flash(void)
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{
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volatile struct stm32l4x_flash *flash =
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(struct stm32l4x_flash *)(FLASH_R_BASE);
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if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 16000000) {
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flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_0;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 32000000) {
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flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_1;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 48000000) {
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flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_2;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) {
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flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_3;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 80000000) {
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flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_4;
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}
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}
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static int pllqrdiv(int val)
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{
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switch (val) {
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case 2:
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return 0;
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case 4:
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return 1;
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case 6:
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return 2;
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case 8:
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return 3;
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}
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return 0;
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}
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static int stm32l4x_clock_control_init(struct device *dev)
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{
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struct stm32l4x_rcc_data *data = dev->driver_data;
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volatile struct stm32l4x_rcc *rcc;
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/* SYSCLK source defaults to MSI */
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int sysclk_src = STM32L4X_RCC_CFG_SYSCLK_SRC_MSI;
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uint32_t hpre = ahb_prescaler(CONFIG_CLOCK_STM32L4X_AHB_PRESCALER);
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uint32_t ppre1 = apb_prescaler(CONFIG_CLOCK_STM32L4X_APB1_PRESCALER);
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uint32_t ppre2 = apb_prescaler(CONFIG_CLOCK_STM32L4X_APB2_PRESCALER);
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#ifdef CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_PLL
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uint32_t pllm = CONFIG_CLOCK_STM32L4X_PLL_DIVISOR-1;
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uint32_t plln = CONFIG_CLOCK_STM32L4X_PLL_MULTIPLIER;
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uint32_t pllpdiv = CONFIG_CLOCK_STM32L4X_PLL_P_DIVISOR;
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uint32_t pllqdiv = pllqrdiv(CONFIG_CLOCK_STM32L4X_PLL_Q_DIVISOR);
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uint32_t pllrdiv = pllqrdiv(CONFIG_CLOCK_STM32L4X_PLL_R_DIVISOR);
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#endif /* CONFIG_CLOCK_STM32L4X_PLL_MULTIPLIER */
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rcc = (struct stm32l4x_rcc *)(data->base);
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/* disable PLL */
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rcc->cr.bit.pllon = 0;
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/* disable HSE */
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rcc->cr.bit.hseon = 0;
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#ifdef CONFIG_CLOCK_STM32L4X_HSE_BYPASS
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/* HSE is disabled, HSE bypass can be enabled*/
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rcc->cr.bit.hsebyp = 1;
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#endif
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#ifdef CONFIG_CLOCK_STM32L4X_PLL_SRC_MSI
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/* enable MSI clock */
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rcc->cr.bit.msion = 1;
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/* this should end after one test */
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while (rcc->cr.bit.msirdy != 1) {
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}
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/* PLL input from HSI/2 = 4MHz */
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rcc->pllcfgr.bit.pllsrc = STM32L4X_RCC_CFG_PLL_SRC_MSI;
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#endif /* CONFIG_CLOCK_STM32L4X_PLL_SRC_MSI */
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#ifdef CONFIG_CLOCK_STM32L4X_PLL_SRC_HSI
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/* wait for to become ready */
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rcc->cr.bit.hsion = 1;
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while (rcc->cr.bit.hsirdy != 1) {
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}
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rcc->pllcfgr.bit.pllsrc = STM32L4X_RCC_CFG_PLL_SRC_HSI;
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#endif /* CONFIG_CLOCK_STM32L4X_PLL_SRC_HSI */
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/* setup AHB prescaler */
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rcc->cfgr.bit.hpre = hpre;
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/* setup APB1, must not exceed 36MHz */
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rcc->cfgr.bit.ppre1 = ppre1;
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/* setup APB2 */
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rcc->cfgr.bit.ppre2 = ppre2;
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#ifdef CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_PLL
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/* setup PLL multiplication and divisor (PLL must be disabled) */
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rcc->pllcfgr.bit.pllm = pllm;
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rcc->pllcfgr.bit.plln = plln;
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/* Setup PLL output divisors */
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rcc->pllcfgr.bit.pllp = pllpdiv == 17 ? 1 : 0;
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rcc->pllcfgr.bit.pllpen = !!pllpdiv;
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rcc->pllcfgr.bit.pllq = pllqdiv;
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rcc->pllcfgr.bit.pllqen = !!CONFIG_CLOCK_STM32L4X_PLL_Q_DIVISOR;
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rcc->pllcfgr.bit.pllr = pllrdiv;
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rcc->pllcfgr.bit.pllren = !!CONFIG_CLOCK_STM32L4X_PLL_R_DIVISOR;
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/* enable PLL */
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rcc->cr.bit.pllon = 1;
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/* wait for PLL to become ready */
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while (rcc->cr.bit.pllrdy != 1) {
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}
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sysclk_src = STM32L4X_RCC_CFG_SYSCLK_SRC_PLL;
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#elif defined(CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_HSE)
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/* wait for to become ready */
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rcc->cr.bit.hseon = 1;
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while (rcc->cr.bit.hserdy != 1) {
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}
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sysclk_src = STM32L4X_RCC_CFG_SYSCLK_SRC_HSE;
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#else
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#error "Need to select or implement support for this STM32L4X SYSCLK source"
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#endif
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/* configure flash access latency before SYSCLK source
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* switch
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*/
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setup_flash();
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/* set SYSCLK clock value */
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rcc->cfgr.bit.sw = sysclk_src;
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/* wait for SYSCLK to switch the source */
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while (rcc->cfgr.bit.sws != sysclk_src) {
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}
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return 0;
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}
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static struct stm32l4x_rcc_data stm32l4x_rcc_data = {
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.base = (uint8_t *)RCC_BASE,
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};
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_AND_API_INIT(rcc_stm32l4x, STM32_CLOCK_CONTROL_NAME,
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&stm32l4x_clock_control_init,
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&stm32l4x_rcc_data, NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_STM32L4X_DEVICE_INIT_PRIORITY,
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&stm32l4x_clock_control_api);
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