mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-10 03:55:52 +00:00
e9cece87bb
Both AdvA and TargetA have constant offset in extended header so it makes sense to have dedicated definitions for those numbers. AdvA is always placed at the beginning on extended header while TargetA follows AdvA directly. There are no PDUs without AdvA and with only TargetA. Offsets of other fields depends on extended header contents and thus are non constant. Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
732 lines
18 KiB
C
732 lines
18 KiB
C
/*
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* Copyright (c) 2016 Nordic Semiconductor ASA
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* Copyright (c) 2016 Vinayak Kariappa Chettimada
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/*
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* PDU fields sizes
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*/
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#define PDU_PREAMBLE_SIZE(phy) (phy&0x3)
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#define PDU_ACCESS_ADDR_SIZE 4
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#define PDU_HEADER_SIZE 2
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#define PDU_MIC_SIZE 4
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#define PDU_CRC_SIZE 3
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#define PDU_OVERHEAD_SIZE(phy) (PDU_PREAMBLE_SIZE(phy) + \
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PDU_ACCESS_ADDR_SIZE + \
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PDU_HEADER_SIZE + \
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PDU_CRC_SIZE)
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#define BDADDR_SIZE 6
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#define ADVA_SIZE BDADDR_SIZE
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#define SCANA_SIZE BDADDR_SIZE
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#define INITA_SIZE BDADDR_SIZE
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#define TARGETA_SIZE BDADDR_SIZE
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#define LLDATA_SIZE 22
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/* Constant offsets in extended header (TargetA is present in PDUs with AdvA) */
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#define ADVA_OFFSET 0
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#define TGTA_OFFSET (ADVA_OFFSET + BDADDR_SIZE)
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#define BYTES2US(bytes, phy) (((bytes)<<3)/BIT((phy&0x3)>>1))
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/* Advertisement channel maximum legacy payload size */
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#define PDU_AC_LEG_PAYLOAD_SIZE_MAX 37
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/* Advertisement channel maximum extended payload size */
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#define PDU_AC_EXT_PAYLOAD_SIZE_MAX 255
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/* Advertisement channel maximum payload size */
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#if defined(CONFIG_BT_CTLR_ADV_EXT)
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#define PDU_AC_EXT_HEADER_SIZE_MAX 63
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/* TODO: PDU_AC_EXT_PAYLOAD_OVERHEAD can be reduced based on supported
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* features, like omitting support for periodic advertising will reduce
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* 18 octets in the Common Extended Advertising Payload Format.
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*/
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#define PDU_AC_EXT_PAYLOAD_OVERHEAD (offsetof(struct pdu_adv_com_ext_adv, \
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ext_hdr_adv_data) + \
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PDU_AC_EXT_HEADER_SIZE_MAX)
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#define PDU_AC_PAYLOAD_SIZE_MAX MAX(MIN((PDU_AC_EXT_PAYLOAD_OVERHEAD + \
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CONFIG_BT_CTLR_ADV_DATA_LEN_MAX), \
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PDU_AC_EXT_PAYLOAD_SIZE_MAX), \
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PDU_AC_LEG_PAYLOAD_SIZE_MAX)
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#else
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#define PDU_AC_PAYLOAD_SIZE_MAX PDU_AC_LEG_PAYLOAD_SIZE_MAX
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#endif
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/* Link Layer header size of Adv PDU. Assumes pdu_adv is packed */
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#define PDU_AC_LL_HEADER_SIZE (offsetof(struct pdu_adv, payload))
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/* Link Layer Advertisement channel maximum PDU buffer size */
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#define PDU_AC_LL_SIZE_MAX (PDU_AC_LL_HEADER_SIZE + PDU_AC_PAYLOAD_SIZE_MAX)
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/* Advertisement channel maximum legacy advertising/scan data size */
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#define PDU_AC_DATA_SIZE_MAX 31
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/* Advertisement channel Access Address */
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#define PDU_AC_ACCESS_ADDR 0x8e89bed6
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/* Data channel minimum payload size and time */
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#define PDU_DC_PAYLOAD_SIZE_MIN 27
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#define PDU_DC_PAYLOAD_TIME_MIN 328
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/* Link Layer header size of Data PDU. Assumes pdu_data is packed */
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#define PDU_DC_LL_HEADER_SIZE (offsetof(struct pdu_data, lldata))
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/* Link Layer Max size of an empty PDU. TODO: Remove; only used in Nordic LLL */
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#define PDU_EM_LL_SIZE_MAX (PDU_DC_LL_HEADER_SIZE)
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/* Event interframe timings */
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#define EVENT_IFS_US 150
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/* Standard allows 2 us timing uncertainty inside the event */
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#define EVENT_IFS_MAX_US (EVENT_IFS_US + 2)
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/* Controller will layout extended adv with minimum separation */
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#define EVENT_MAFS_US 300
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/* Standard allows 2 us timing uncertainty inside the event */
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#define EVENT_MAFS_MAX_US (EVENT_MAFS_US + 2)
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/* Offset Units field encoding */
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#define OFFS_UNIT_30_US 30
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#define OFFS_UNIT_300_US 300
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/*
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* Macros to return correct Data Channel PDU time
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* Note: formula is valid for 1M, 2M and Coded S8
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* see BT spec Version 5.1 Vol 6. Part B, chapters 2.1 and 2.2
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* for packet formats and thus lengths
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*/
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#define PHY_LEGACY 0
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#define PHY_1M BIT(0)
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#define PHY_2M BIT(1)
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#define PHY_CODED BIT(2)
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#if defined(CONFIG_BT_CTLR_PHY_CODED)
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#define CODED_PHY_PREAMBLE_TIME_US 80
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#define CODED_PHY_ACCESS_ADDRESS_TIME_US 256
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#define CODED_PHY_CI_TIME_US 16
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#define CODED_PHY_TERM1_TIME_US 24
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#define CODED_PHY_CRC_SIZE 24
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#define CODED_PHY_TERM2_SIZE 3
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#define FEC_BLOCK1_TIME_US ((CODED_PHY_ACCESS_ADDRESS_TIME_US) + \
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(CODED_PHY_CI_TIME_US) + \
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(CODED_PHY_TERM1_TIME_US))
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#define FEC_BLOCK2_TIME_US(octets, mic) (((((PDU_HEADER_SIZE) + \
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(octets) + \
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(mic))<<3) + \
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(CODED_PHY_CRC_SIZE) + \
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(CODED_PHY_TERM2_SIZE))<<3)
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#define PKT_DC_US(octets, mic, phy) (((phy) & PHY_CODED) ? \
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((CODED_PHY_PREAMBLE_TIME_US) + \
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(FEC_BLOCK1_TIME_US) + \
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FEC_BLOCK2_TIME_US((octets), (mic))) : \
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(((PDU_PREAMBLE_SIZE(phy) + \
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(PDU_ACCESS_ADDR_SIZE) + \
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(PDU_HEADER_SIZE) + \
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(octets) + \
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(mic) + \
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(PDU_CRC_SIZE))<<3) / \
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BIT(((phy) & 0x03) >> 1)))
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#else /* !CONFIG_BT_CTLR_PHY_CODED */
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#define PKT_DC_US(octets, mic, phy) (((PDU_PREAMBLE_SIZE(phy) + \
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(PDU_ACCESS_ADDR_SIZE) + \
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(PDU_HEADER_SIZE) + \
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(octets) + \
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(mic) + \
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(PDU_CRC_SIZE))<<3) / \
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BIT(((phy) & 0x03) >> 1))
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#endif /* !CONFIG_BT_CTLR_PHY_CODED */
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#define PKT_US(octets, phy) PKT_DC_US((octets), (PDU_MIC_SIZE), (phy))
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#define PKT_AC_US(octets, mic, phy) PKT_DC_US((octets), (mic), (phy))
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/* Extra bytes for enqueued node_rx metadata: rssi (always), resolving
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* index, directed adv report, and mesh channel and instant.
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*/
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#define PDU_AC_SIZE_RSSI 1
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#if defined(CONFIG_BT_CTLR_PRIVACY)
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#define PDU_AC_SIZE_PRIV 1
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#else
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#define PDU_AC_SIZE_PRIV 0
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#endif /* CONFIG_BT_CTLR_PRIVACY */
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#if defined(CONFIG_BT_CTLR_EXT_SCAN_FP)
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#define PDU_AC_SIZE_SCFP 1
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#else
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#define PDU_AC_SIZE_SCFP 0
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#endif /* CONFIG_BT_CTLR_EXT_SCAN_FP */
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#if defined(CONFIG_BT_HCI_MESH_EXT)
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#define PDU_AC_SIZE_MESH 5
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#else
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#define PDU_AC_SIZE_MESH 0
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#endif /* CONFIG_BT_HCI_MESH_EXT */
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#define PDU_AC_LL_SIZE_EXTRA (PDU_AC_SIZE_RSSI + \
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PDU_AC_SIZE_PRIV + \
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PDU_AC_SIZE_SCFP + \
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PDU_AC_SIZE_MESH)
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struct pdu_adv_adv_ind {
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uint8_t addr[BDADDR_SIZE];
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uint8_t data[PDU_AC_DATA_SIZE_MAX];
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} __packed;
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struct pdu_adv_direct_ind {
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uint8_t adv_addr[BDADDR_SIZE];
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uint8_t tgt_addr[BDADDR_SIZE];
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} __packed;
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struct pdu_adv_scan_rsp {
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uint8_t addr[BDADDR_SIZE];
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uint8_t data[PDU_AC_DATA_SIZE_MAX];
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} __packed;
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struct pdu_adv_scan_req {
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uint8_t scan_addr[BDADDR_SIZE];
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uint8_t adv_addr[BDADDR_SIZE];
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} __packed;
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struct pdu_adv_connect_ind {
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uint8_t init_addr[BDADDR_SIZE];
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uint8_t adv_addr[BDADDR_SIZE];
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struct {
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uint8_t access_addr[4];
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uint8_t crc_init[3];
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uint8_t win_size;
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uint16_t win_offset;
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uint16_t interval;
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uint16_t latency;
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uint16_t timeout;
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uint8_t chan_map[5];
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint8_t hop:5;
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uint8_t sca:3;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint8_t sca:3;
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uint8_t hop:5;
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#else
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#error "Unsupported endianness"
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#endif
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} __packed;
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} __packed;
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struct pdu_adv_ext_hdr {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint8_t adv_addr:1;
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uint8_t tgt_addr:1;
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uint8_t rfu0:1;
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uint8_t adi:1;
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uint8_t aux_ptr:1;
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uint8_t sync_info:1;
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uint8_t tx_pwr:1;
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uint8_t rfu1:1;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint8_t rfu1:1;
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uint8_t tx_pwr:1;
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uint8_t sync_info:1;
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uint8_t aux_ptr:1;
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uint8_t adi:1;
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uint8_t rfu0:1;
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uint8_t tgt_addr:1;
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uint8_t adv_addr:1;
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#else
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#error "Unsupported endianness"
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#endif
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uint8_t data[0];
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} __packed;
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struct pdu_adv_com_ext_adv {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint8_t ext_hdr_len:6;
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uint8_t adv_mode:2;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint8_t adv_mode:2;
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uint8_t ext_hdr_len:6;
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#else
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#error "Unsupported endianness"
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#endif
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union {
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struct pdu_adv_ext_hdr ext_hdr;
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uint8_t ext_hdr_adv_data[254];
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};
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} __packed;
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enum pdu_adv_mode {
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EXT_ADV_MODE_NON_CONN_NON_SCAN = 0x00,
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EXT_ADV_MODE_CONN_NON_SCAN = 0x01,
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EXT_ADV_MODE_NON_CONN_SCAN = 0x02,
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};
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struct pdu_adv_adi {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint16_t did:12;
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uint16_t sid:4;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint16_t sid:4;
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uint16_t did:12;
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#else
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#error "Unsupported endianness"
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#endif
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} __packed;
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struct pdu_adv_aux_ptr {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint8_t chan_idx:6;
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uint8_t ca:1;
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uint8_t offs_units:1;
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uint16_t offs:13;
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uint16_t phy:3;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint8_t offs_units:1;
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uint8_t ca:1;
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uint8_t chan_idx:6;
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uint16_t phy:3;
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uint16_t offs:13;
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#else
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#error "Unsupported endianness"
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#endif
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} __packed;
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enum pdu_adv_aux_ptr_ca {
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EXT_ADV_AUX_PTR_CA_500_PPM = 0x00,
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EXT_ADV_AUX_PTR_CA_50_PPM = 0x01,
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};
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enum pdu_adv_offs_units {
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EXT_ADV_AUX_PTR_OFFS_UNITS_30 = 0x00,
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EXT_ADV_AUX_PTR_OFFS_UNITS_300 = 0x01,
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};
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enum pdu_adv_aux_phy {
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EXT_ADV_AUX_PHY_LE_1M = 0x00,
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EXT_ADV_AUX_PHY_LE_2M = 0x01,
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EXT_ADV_AUX_PHY_LE_COD = 0x02,
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};
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struct pdu_adv_sync_info {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint16_t offs:13;
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uint16_t offs_units:1;
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uint16_t rfu:2;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint16_t rfu:2;
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uint16_t offs_units:1;
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uint16_t offs:13;
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#else
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#error "Unsupported endianness"
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#endif
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uint16_t interval;
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uint8_t sca_chm[5];
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uint32_t aa;
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uint8_t crc_init[3];
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uint16_t evt_cntr;
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} __packed;
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enum pdu_adv_type {
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PDU_ADV_TYPE_ADV_IND = 0x00,
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PDU_ADV_TYPE_DIRECT_IND = 0x01,
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PDU_ADV_TYPE_NONCONN_IND = 0x02,
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PDU_ADV_TYPE_SCAN_REQ = 0x03,
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PDU_ADV_TYPE_AUX_SCAN_REQ = PDU_ADV_TYPE_SCAN_REQ,
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PDU_ADV_TYPE_SCAN_RSP = 0x04,
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PDU_ADV_TYPE_ADV_IND_SCAN_RSP = 0x05,
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PDU_ADV_TYPE_CONNECT_IND = 0x05,
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PDU_ADV_TYPE_AUX_CONNECT_REQ = PDU_ADV_TYPE_CONNECT_IND,
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PDU_ADV_TYPE_SCAN_IND = 0x06,
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PDU_ADV_TYPE_EXT_IND = 0x07,
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PDU_ADV_TYPE_AUX_ADV_IND = PDU_ADV_TYPE_EXT_IND,
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PDU_ADV_TYPE_AUX_SCAN_RSP = PDU_ADV_TYPE_EXT_IND,
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PDU_ADV_TYPE_AUX_SYNC_IND = PDU_ADV_TYPE_EXT_IND,
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PDU_ADV_TYPE_AUX_CHAIN_IND = PDU_ADV_TYPE_EXT_IND,
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PDU_ADV_TYPE_AUX_CONNECT_RSP = 0x08,
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} __packed;
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struct pdu_adv {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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uint8_t type:4;
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uint8_t rfu:1;
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uint8_t chan_sel:1;
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uint8_t tx_addr:1;
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uint8_t rx_addr:1;
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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uint8_t rx_addr:1;
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uint8_t tx_addr:1;
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uint8_t chan_sel:1;
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uint8_t rfu:1;
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uint8_t type:4;
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#else
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#error "Unsupported endianness"
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#endif
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uint8_t len;
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union {
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uint8_t payload[0];
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struct pdu_adv_adv_ind adv_ind;
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struct pdu_adv_direct_ind direct_ind;
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struct pdu_adv_scan_req scan_req;
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struct pdu_adv_scan_rsp scan_rsp;
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struct pdu_adv_connect_ind connect_ind;
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#if defined(CONFIG_BT_CTLR_ADV_EXT)
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struct pdu_adv_com_ext_adv adv_ext_ind;
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#endif /* CONFIG_BT_CTLR_ADV_EXT */
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} __packed;
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} __packed;
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enum pdu_data_llid {
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PDU_DATA_LLID_RESV = 0x00,
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PDU_DATA_LLID_DATA_CONTINUE = 0x01,
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PDU_DATA_LLID_DATA_START = 0x02,
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PDU_DATA_LLID_CTRL = 0x03,
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};
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enum pdu_data_llctrl_type {
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PDU_DATA_LLCTRL_TYPE_CONN_UPDATE_IND = 0x00,
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PDU_DATA_LLCTRL_TYPE_CHAN_MAP_IND = 0x01,
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PDU_DATA_LLCTRL_TYPE_TERMINATE_IND = 0x02,
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PDU_DATA_LLCTRL_TYPE_ENC_REQ = 0x03,
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PDU_DATA_LLCTRL_TYPE_ENC_RSP = 0x04,
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PDU_DATA_LLCTRL_TYPE_START_ENC_REQ = 0x05,
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PDU_DATA_LLCTRL_TYPE_START_ENC_RSP = 0x06,
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PDU_DATA_LLCTRL_TYPE_UNKNOWN_RSP = 0x07,
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PDU_DATA_LLCTRL_TYPE_FEATURE_REQ = 0x08,
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PDU_DATA_LLCTRL_TYPE_FEATURE_RSP = 0x09,
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PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_REQ = 0x0A,
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PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_RSP = 0x0B,
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PDU_DATA_LLCTRL_TYPE_VERSION_IND = 0x0C,
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PDU_DATA_LLCTRL_TYPE_REJECT_IND = 0x0D,
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PDU_DATA_LLCTRL_TYPE_SLAVE_FEATURE_REQ = 0x0E,
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PDU_DATA_LLCTRL_TYPE_CONN_PARAM_REQ = 0x0F,
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PDU_DATA_LLCTRL_TYPE_CONN_PARAM_RSP = 0x10,
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PDU_DATA_LLCTRL_TYPE_REJECT_EXT_IND = 0x11,
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PDU_DATA_LLCTRL_TYPE_PING_REQ = 0x12,
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PDU_DATA_LLCTRL_TYPE_PING_RSP = 0x13,
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PDU_DATA_LLCTRL_TYPE_LENGTH_REQ = 0x14,
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PDU_DATA_LLCTRL_TYPE_LENGTH_RSP = 0x15,
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PDU_DATA_LLCTRL_TYPE_PHY_REQ = 0x16,
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PDU_DATA_LLCTRL_TYPE_PHY_RSP = 0x17,
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PDU_DATA_LLCTRL_TYPE_PHY_UPD_IND = 0x18,
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PDU_DATA_LLCTRL_TYPE_MIN_USED_CHAN_IND = 0x19,
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};
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struct pdu_data_llctrl_conn_update_ind {
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uint8_t win_size;
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uint16_t win_offset;
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uint16_t interval;
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uint16_t latency;
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uint16_t timeout;
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uint16_t instant;
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} __packed;
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struct pdu_data_llctrl_chan_map_ind {
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uint8_t chm[5];
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uint16_t instant;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_terminate_ind {
|
|
uint8_t error_code;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_enc_req {
|
|
uint8_t rand[8];
|
|
uint8_t ediv[2];
|
|
uint8_t skdm[8];
|
|
uint8_t ivm[4];
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_enc_rsp {
|
|
uint8_t skds[8];
|
|
uint8_t ivs[4];
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_start_enc_req {
|
|
/* no members */
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_start_enc_rsp {
|
|
/* no members */
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_unknown_rsp {
|
|
uint8_t type;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_feature_req {
|
|
uint8_t features[8];
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_feature_rsp {
|
|
uint8_t features[8];
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_pause_enc_req {
|
|
/* no members */
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_pause_enc_rsp {
|
|
/* no members */
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_version_ind {
|
|
uint8_t version_number;
|
|
uint16_t company_id;
|
|
uint16_t sub_version_number;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_reject_ind {
|
|
uint8_t error_code;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_slave_feature_req {
|
|
uint8_t features[8];
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_conn_param_req {
|
|
uint16_t interval_min;
|
|
uint16_t interval_max;
|
|
uint16_t latency;
|
|
uint16_t timeout;
|
|
uint8_t preferred_periodicity;
|
|
uint16_t reference_conn_event_count;
|
|
uint16_t offset0;
|
|
uint16_t offset1;
|
|
uint16_t offset2;
|
|
uint16_t offset3;
|
|
uint16_t offset4;
|
|
uint16_t offset5;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_conn_param_rsp {
|
|
uint16_t interval_min;
|
|
uint16_t interval_max;
|
|
uint16_t latency;
|
|
uint16_t timeout;
|
|
uint8_t preferred_periodicity;
|
|
uint16_t reference_conn_event_count;
|
|
uint16_t offset0;
|
|
uint16_t offset1;
|
|
uint16_t offset2;
|
|
uint16_t offset3;
|
|
uint16_t offset4;
|
|
uint16_t offset5;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_reject_ext_ind {
|
|
uint8_t reject_opcode;
|
|
uint8_t error_code;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_ping_req {
|
|
/* no members */
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_ping_rsp {
|
|
/* no members */
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_length_req {
|
|
uint16_t max_rx_octets;
|
|
uint16_t max_rx_time;
|
|
uint16_t max_tx_octets;
|
|
uint16_t max_tx_time;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_length_rsp {
|
|
uint16_t max_rx_octets;
|
|
uint16_t max_rx_time;
|
|
uint16_t max_tx_octets;
|
|
uint16_t max_tx_time;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_phy_req {
|
|
uint8_t tx_phys;
|
|
uint8_t rx_phys;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_phy_rsp {
|
|
uint8_t tx_phys;
|
|
uint8_t rx_phys;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_phy_upd_ind {
|
|
uint8_t m_to_s_phy;
|
|
uint8_t s_to_m_phy;
|
|
uint16_t instant;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl_min_used_chans_ind {
|
|
uint8_t phys;
|
|
uint8_t min_used_chans;
|
|
} __packed;
|
|
|
|
struct pdu_data_llctrl {
|
|
uint8_t opcode;
|
|
union {
|
|
struct pdu_data_llctrl_conn_update_ind conn_update_ind;
|
|
struct pdu_data_llctrl_chan_map_ind chan_map_ind;
|
|
struct pdu_data_llctrl_terminate_ind terminate_ind;
|
|
struct pdu_data_llctrl_enc_req enc_req;
|
|
struct pdu_data_llctrl_enc_rsp enc_rsp;
|
|
struct pdu_data_llctrl_start_enc_req start_enc_req;
|
|
struct pdu_data_llctrl_start_enc_rsp start_enc_rsp;
|
|
struct pdu_data_llctrl_unknown_rsp unknown_rsp;
|
|
struct pdu_data_llctrl_feature_req feature_req;
|
|
struct pdu_data_llctrl_feature_rsp feature_rsp;
|
|
struct pdu_data_llctrl_pause_enc_req pause_enc_req;
|
|
struct pdu_data_llctrl_pause_enc_rsp pause_enc_rsp;
|
|
struct pdu_data_llctrl_version_ind version_ind;
|
|
struct pdu_data_llctrl_reject_ind reject_ind;
|
|
struct pdu_data_llctrl_slave_feature_req slave_feature_req;
|
|
struct pdu_data_llctrl_conn_param_req conn_param_req;
|
|
struct pdu_data_llctrl_conn_param_rsp conn_param_rsp;
|
|
struct pdu_data_llctrl_reject_ext_ind reject_ext_ind;
|
|
struct pdu_data_llctrl_ping_req ping_req;
|
|
struct pdu_data_llctrl_ping_rsp ping_rsp;
|
|
struct pdu_data_llctrl_length_req length_req;
|
|
struct pdu_data_llctrl_length_rsp length_rsp;
|
|
struct pdu_data_llctrl_phy_req phy_req;
|
|
struct pdu_data_llctrl_phy_rsp phy_rsp;
|
|
struct pdu_data_llctrl_phy_upd_ind phy_upd_ind;
|
|
struct pdu_data_llctrl_min_used_chans_ind min_used_chans_ind;
|
|
} __packed;
|
|
} __packed;
|
|
|
|
#if defined(CONFIG_BT_CTLR_PROFILE_ISR)
|
|
struct profile {
|
|
uint8_t lcur;
|
|
uint8_t lmin;
|
|
uint8_t lmax;
|
|
uint8_t cur;
|
|
uint8_t min;
|
|
uint8_t max;
|
|
} __packed;
|
|
#endif /* CONFIG_BT_CTLR_PROFILE_ISR */
|
|
|
|
struct pdu_data {
|
|
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
|
uint8_t ll_id:2;
|
|
uint8_t nesn:1;
|
|
uint8_t sn:1;
|
|
uint8_t md:1;
|
|
uint8_t rfu:3;
|
|
#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
|
uint8_t rfu:3;
|
|
uint8_t md:1;
|
|
uint8_t sn:1;
|
|
uint8_t nesn:1;
|
|
uint8_t ll_id:2;
|
|
#else
|
|
#error "Unsupported endianness"
|
|
#endif
|
|
|
|
uint8_t len;
|
|
|
|
#if !defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
|
|
#if !defined(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR)
|
|
uint8_t resv:8; /* TODO: remove nRF specific code */
|
|
#endif /* !CONFIG_BT_CTLR_DATA_LENGTH_CLEAR */
|
|
#endif /* !CONFIG_SOC_OPENISA_RV32M1_RISCV32 */
|
|
|
|
union {
|
|
struct pdu_data_llctrl llctrl;
|
|
uint8_t lldata[0];
|
|
|
|
#if defined(CONFIG_BT_CTLR_CONN_RSSI)
|
|
uint8_t rssi;
|
|
#endif /* CONFIG_BT_CTLR_CONN_RSSI */
|
|
|
|
#if defined(CONFIG_BT_CTLR_PROFILE_ISR)
|
|
struct profile profile;
|
|
#endif /* CONFIG_BT_CTLR_PROFILE_ISR */
|
|
} __packed;
|
|
} __packed;
|
|
|
|
struct pdu_cis {
|
|
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
|
uint8_t ll_id:2;
|
|
uint8_t nesn:1;
|
|
uint8_t sn:1;
|
|
uint8_t cie:1;
|
|
uint8_t rfu0:1;
|
|
uint8_t npi:1;
|
|
uint8_t rfu1:1;
|
|
#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
|
uint8_t rfu1:1;
|
|
uint8_t npi:1;
|
|
uint8_t rfu0:1;
|
|
uint8_t cie:1;
|
|
uint8_t sn:1;
|
|
uint8_t nesn:1;
|
|
uint8_t ll_id:2;
|
|
#else
|
|
#error "Unsupported endianness"
|
|
#endif /* __BYTE_ORDER__ */
|
|
uint8_t length;
|
|
uint8_t payload[0];
|
|
} __packed;
|
|
|
|
enum pdu_big_ctrl_type {
|
|
PDU_BIG_CTRL_TYPE_CHAN_MAP_IND = 0x00,
|
|
PDU_BIG_CTRL_TYPE_TERM_IND = 0x01,
|
|
};
|
|
|
|
struct pdu_big_ctrl_chan_map_ind {
|
|
uint8_t chm[5];
|
|
uint16_t instant;
|
|
} __packed;
|
|
|
|
struct pdu_big_ctrl_term_ind {
|
|
uint8_t reason;
|
|
uint16_t instant;
|
|
} __packed;
|
|
|
|
|
|
struct pdu_big_ctrl {
|
|
uint8_t opcode;
|
|
union {
|
|
uint8_t ctrl_data[0];
|
|
struct pdu_big_ctrl_chan_map_ind chan_map_ind;
|
|
struct pdu_big_ctrl_term_ind term_ind;
|
|
} __packed;
|
|
} __packed;
|
|
|
|
enum pdu_bis_llid {
|
|
/** Unframed complete or end fragment */
|
|
PDU_BIS_LLID_COMPLETE_END = 0x00,
|
|
/** Unframed start or continuation fragment */
|
|
PDU_BIS_LLID_START_CONTINUE = 0x01,
|
|
/** Framed; one or more segments of a SDU */
|
|
PDU_BIS_LLID_FRAMED = 0x02,
|
|
/** BIG Control PDU */
|
|
PDU_BIS_LLID_CTRL = 0x03,
|
|
};
|
|
|
|
struct pdu_bis {
|
|
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
|
uint8_t ll_id:2;
|
|
uint8_t cssn:3;
|
|
uint8_t cstf:1;
|
|
uint8_t rfu:2;
|
|
#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
|
uint8_t rfu:2;
|
|
uint8_t cstf:1;
|
|
uint8_t cssn:3;
|
|
uint8_t ll_id:2;
|
|
#else
|
|
#error "Unsupported endianness"
|
|
#endif /* __BYTE_ORDER__ */
|
|
uint8_t length;
|
|
union {
|
|
uint8_t payload[0];
|
|
struct pdu_big_ctrl ctrl;
|
|
} __packed;
|
|
} __packed;
|