mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 00:51:57 +00:00
55caa7b743
Makes the designware spi driver consistent with other spi drivers by selecting HAS_DTS_SPI in the driver. This required adding spi nodes and dts fixups to several arc and x86 socs, as well as enabling those nodes in associated boards. Also refactors the driver to use the base address, interrupt number, and interrupt priority from dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
124 lines
2.4 KiB
Plaintext
124 lines
2.4 KiB
Plaintext
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/intel-mvic.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,quark";
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reg = <0>;
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};
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intc: mvic {
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compatible = "intel,mvic";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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flash0: flash@180000 {
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compatible = "soc-nv-flash";
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reg = <0x00180000 DT_FLASH_SIZE>;
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};
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sram0: memory@280000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00280000 DT_SRAM_SIZE>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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rtc: rtc@b0000400 {
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compatible = "intel,qmsi-rtc";
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reg = <0xb0000400 0x400>;
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clock-frequency = <32768>;
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interrupts = <2 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&intc>;
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label = "RTC_0";
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};
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uart0: uart@b0002000 {
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compatible = "intel,qmsi-uart";
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reg = <0xb0002000 0x400>;
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label = "UART_0";
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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uart1: uart@b0002400 {
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compatible = "intel,qmsi-uart";
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reg = <0xb0002400 0x400>;
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label = "UART_1";
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interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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gpio: gpio@b0000c00 {
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compatible = "intel,qmsi-gpio";
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reg = <0xb0000c00 0x400>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@b0002800 {
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compatible = "intel,qmsi-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0002800 0x400>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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label = "I2C_0";
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status = "disabled";
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};
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adc0: adc@b0004000 {
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compatible = "intel,quark-d2000-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xB0004000 0x3F>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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label = "ADC_0";
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status = "disabled";
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};
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spi0: spi@b0001000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0001000 0x400>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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label = "SPI_0";
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status = "disabled";
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};
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};
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};
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