Daniel Leung 7bb5015ced tests: benchmarks: use high-res counter for MEC1501 SoC ... The timer counter for ticks on MEC1501 SoC is based on the RTOS timer which runs at 32kHz. This is too slow for timing benchmarks as most cases can be finished within one or two ticks. Since the SoC has higher frequency timers running at 48MHz, add the necessary bits to use these for timing benchmarks. Fix #23414 Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2020-03-31 19:52:21 -04:00
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CMakeLists.txt	arch: common: Delete isr_tables.ld which was a copy of intlist.ld	2020-01-30 14:19:14 -05:00
gen_isr_tables.py	gen_isr_tables: Improve error message	2020-01-29 14:21:00 -08:00
isr_tables.c	isr_tables: Support hardware interrupt vector table-only configuration.	2020-03-13 12:02:03 +01:00
nocache.ld
ramfunc.ld
sw_isr_common.c	interrupts: Do not assert on IRQ enable status for ISR install on GIC	2020-03-31 19:24:48 +02:00
text_section_offset.ld
timing_info_bench.c	tests: benchmarks: use high-res counter for MEC1501 SoC	2020-03-31 19:52:21 -04:00