mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-12 10:17:10 +00:00
7e0eed9235
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/*
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* Copyright (c) 2019 Aurelien Jarno
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_pwm
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#include <device.h>
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#include <errno.h>
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#include <drivers/pwm.h>
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#include <soc.h>
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#define LOG_LEVEL CONFIG_PWM_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_sam);
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struct sam_pwm_config {
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Pwm *regs;
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u32_t id;
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u8_t prescaler;
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u8_t divider;
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};
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#define DEV_CFG(dev) \
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((const struct sam_pwm_config * const)(dev)->config_info)
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static int sam_pwm_get_cycles_per_sec(struct device *dev, u32_t pwm,
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u64_t *cycles)
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{
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u8_t prescaler = DEV_CFG(dev)->prescaler;
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u8_t divider = DEV_CFG(dev)->divider;
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*cycles = SOC_ATMEL_SAM_MCK_FREQ_HZ /
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((1 << prescaler) * divider);
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return 0;
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}
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static int sam_pwm_pin_set(struct device *dev, u32_t ch,
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u32_t period_cycles, u32_t pulse_cycles,
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pwm_flags_t flags)
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{
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Pwm *const pwm = DEV_CFG(dev)->regs;
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if (ch >= PWMCHNUM_NUMBER) {
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return -EINVAL;
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}
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if (flags) {
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/* PWM polarity not supported (yet?) */
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return -ENOTSUP;
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}
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if (period_cycles == 0U || pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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if (period_cycles > 0xffff) {
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return -ENOTSUP;
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}
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/* Select clock A */
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pwm->PWM_CH_NUM[ch].PWM_CMR = PWM_CMR_CPRE_CLKA_Val;
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/* Update period and pulse using the update registers, so that the
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* change is triggered at the next PWM period.
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*/
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pwm->PWM_CH_NUM[ch].PWM_CPRDUPD = period_cycles;
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pwm->PWM_CH_NUM[ch].PWM_CDTYUPD = pulse_cycles;
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/* Enable the output */
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pwm->PWM_ENA = 1 << ch;
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return 0;
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}
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static int sam_pwm_init(struct device *dev)
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{
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Pwm *const pwm = DEV_CFG(dev)->regs;
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u32_t id = DEV_CFG(dev)->id;
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u8_t prescaler = DEV_CFG(dev)->prescaler;
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u8_t divider = DEV_CFG(dev)->divider;
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/* FIXME: way to validate prescaler & divider */
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/* Enable the PWM peripheral */
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soc_pmc_peripheral_enable(id);
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/* Configure the clock A that will be used by all 4 channels */
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pwm->PWM_CLK = PWM_CLK_PREA(prescaler) | PWM_CLK_DIVA(divider);
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return 0;
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}
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static const struct pwm_driver_api sam_pwm_driver_api = {
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.pin_set = sam_pwm_pin_set,
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.get_cycles_per_sec = sam_pwm_get_cycles_per_sec,
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};
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#define SAM_INST_INIT(inst) \
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static const struct sam_pwm_config sam_pwm_config_##inst = { \
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.regs = (Pwm *)DT_INST_REG_ADDR(inst), \
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.id = DT_INST_PROP(inst, peripheral_id), \
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.prescaler = DT_INST_PROP(inst, prescaler), \
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.divider = DT_INST_PROP(inst, divider), \
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}; \
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\
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DEVICE_AND_API_INIT(sam_pwm_##inst, DT_INST_LABEL(inst), \
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&sam_pwm_init, \
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NULL, &sam_pwm_config_##inst, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&sam_pwm_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(SAM_INST_INIT)
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