mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-06 17:12:14 +00:00
620ff636d4
Fix issue #9028: last bit of SPI/I2S transaction may be corrupted. Impacted STM32 SOC series: F0/F1/F2/F3/F4/L0. Notes: - F2/F4/L0: set gpio to very_high speed ('11') - F0/F3: set gpio to high speed ('11'). - F1: set gpio to 50MHz. Signed-off-by: Armando Visconti <armando.visconti@st.com>
74 lines
3.2 KiB
C
74 lines
3.2 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F1_H_
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#define ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F1_H_
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/**
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* @file Header for STM32F1 pin multiplexing helper
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*/
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/*
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* Note:
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* The SPIx_SCK pin speed must be set to 50MHz ('11') to avoid last data bit
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* corruption which is a known issue of STM32F1 SPI peripheral (see errata
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* sheets).
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*/
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#define STM32F1_PINMUX_FUNC_PA9_USART1_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PA10_USART1_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA2_USART2_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PA3_USART2_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS STM32_PIN_SPI_MASTER_NSS
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#define STM32F1_PINMUX_FUNC_PA4_SPI1_MASTER_NSS_OE STM32_PIN_SPI_MASTER_NSS_OE
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#define STM32F1_PINMUX_FUNC_PA4_SPI1_SLAVE_NSS STM32_PIN_SPI_SLAVE_NSS
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#define STM32F1_PINMUX_FUNC_PA5_SPI1_MASTER_SCK STM32_PIN_SPI_MASTER_SCK | \
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STM32_MODE_OUTPUT_MAX_50
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#define STM32F1_PINMUX_FUNC_PA5_SPI1_SLAVE_SCK STM32_PIN_SPI_SLAVE_SCK | \
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STM32_MODE_OUTPUT_MAX_50
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#define STM32F1_PINMUX_FUNC_PA6_SPI1_MASTER_MISO STM32_PIN_SPI_MASTER_MISO
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#define STM32F1_PINMUX_FUNC_PA6_SPI1_SLAVE_MISO STM32_PIN_SPI_SLAVE_MISO
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#define STM32F1_PINMUX_FUNC_PA7_SPI1_MASTER_MOSI STM32_PIN_SPI_MASTER_MOSI
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#define STM32F1_PINMUX_FUNC_PA7_SPI1_SLAVE_MOSI STM32_PIN_SPI_SLAVE_MOSI
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#define STM32F1_PINMUX_FUNC_PA11_USB_DM STM32_PIN_USB
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#define STM32F1_PINMUX_FUNC_PA12_USB_DP STM32_PIN_USB
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#define STM32F1_PINMUX_FUNC_PD5_USART2_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PD6_USART2_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PB6_I2C1_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB7_I2C1_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB8_I2C1_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB9_I2C1_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB10_USART3_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PB11_USART3_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PC10_UART4_TX STM32_PIN_USART_TX
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#define STM32F1_PINMUX_FUNC_PC11_UART4_RX STM32_PIN_USART_RX
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#define STM32F1_PINMUX_FUNC_PB10_I2C2_SCL STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB11_I2C2_SDA STM32_PIN_I2C
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#define STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS STM32_PIN_SPI_MASTER_NSS
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#define STM32F1_PINMUX_FUNC_PB12_SPI2_MASTER_NSS_OE STM32_PIN_SPI_MASTER_NSS_OE
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#define STM32F1_PINMUX_FUNC_PB12_SPI2_SLAVE_NSS STM32_PIN_SPI_SLAVE_NSS
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#define STM32F1_PINMUX_FUNC_PB13_SPI2_MASTER_SCK STM32_PIN_SPI_MASTER_SCK | \
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STM32_MODE_OUTPUT_MAX_50
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#define STM32F1_PINMUX_FUNC_PB13_SPI2_SLAVE_SCK STM32_PIN_SPI_SLAVE_SCK | \
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STM32_MODE_OUTPUT_MAX_50
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#define STM32F1_PINMUX_FUNC_PB14_SPI2_MASTER_MISO STM32_PIN_SPI_MASTER_MISO
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#define STM32F1_PINMUX_FUNC_PB14_SPI2_SLAVE_MISO STM32_PIN_SPI_SLAVE_MISO
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#define STM32F1_PINMUX_FUNC_PB15_SPI2_MASTER_MOSI STM32_PIN_SPI_MASTER_MOSI
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#define STM32F1_PINMUX_FUNC_PB15_SPI2_SLAVE_MOSI STM32_PIN_SPI_SLAVE_MOSI
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#define STM32F1_PINMUX_FUNC_PA8_PWM1_CH1 STM32_PIN_PWM
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#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F1_H_ */
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