Flavio Ceolin 7f48e992e8 soc: efm32wg: Select SOC_GECKO_CORE if pm is enabled ... Power management requires core interrupt handling. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>		2021-01-22 09:31:20 -05:00
..
arc	cache: Rename CACHE_FLUSHING to CACHE_MANAGEMENT	2021-01-19 14:31:02 -05:00
arm	soc: efm32wg: Select SOC_GECKO_CORE if pm is enabled	2021-01-22 09:31:20 -05:00
nios2
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	soc/riscv: add the QEMU "RISC-V VirtIO board"	2021-01-15 13:06:33 -05:00
sparc
x86	Revert "x86: reserve the first megabyte"	2021-01-22 08:39:45 -05:00
xtensa	tests: common: fix kernel.common test case build fail in intel_adsp_cavs	2021-01-21 14:47:31 -05:00
Kconfig