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FE310 is the name of one SoC out of a range of products in the SiFive Freedom line. The FE310 SoC port in Zephyr is compatible with all of these products, so rename the SoC to SiFive Freedom Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
75 lines
1.9 KiB
Plaintext
75 lines
1.9 KiB
Plaintext
# Kconfig.fe310 - SiFive Freedom UART configuration option
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#
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# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig UART_SIFIVE
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bool "SiFive Freedom serial driver"
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depends on SOC_RISCV32_SIFIVE_FREEDOM
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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help
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This option enables the SiFive Freedom serial driver.
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# ---------- Port 0 ----------
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menuconfig UART_SIFIVE_PORT_0
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bool "Enable SIFIVE Port 0"
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depends on UART_SIFIVE
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help
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This tells the driver to configure the UART port at boot, depending on
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the additional configure options below.
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config UART_SIFIVE_PORT_0_IRQ_PRIORITY
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int "Port 0 Interrupt Priority"
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default 1
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depends on UART_SIFIVE_PORT_0
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help
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Port 0 Interrupt Priority
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config UART_SIFIVE_PORT_0_RXCNT_IRQ
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int "Port 0 RX Interrupt Threshold Count"
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default 0
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depends on UART_SIFIVE_PORT_0
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help
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Port 0 RX Threshold at which the RX FIFO interrupt triggers.
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config UART_SIFIVE_PORT_0_TXCNT_IRQ
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int "Port 0 TX Interrupt Threshold Count"
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default 0
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depends on UART_SIFIVE_PORT_0
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help
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Port 0 TX Threshold at which the TX FIFO interrupt triggers.
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# ---------- Port 1 ----------
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menuconfig UART_SIFIVE_PORT_1
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bool "Enable SIFIVE Port 1"
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depends on UART_SIFIVE
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help
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This tells the driver to configure the UART port at boot, depending on
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the additional configure options below.
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config UART_SIFIVE_PORT_1_IRQ_PRIORITY
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int "Port 1 Interrupt Priority"
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default 1
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depends on UART_SIFIVE_PORT_1
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help
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Port 1 Interrupt Priority
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config UART_SIFIVE_PORT_1_RXCNT_IRQ
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int "Port 0 RX Interrupt Threshold Count"
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default 0
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depends on UART_SIFIVE_PORT_1
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help
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Port 1 RX Threshold at which the RX FIFO interrupt triggers.
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config UART_SIFIVE_PORT_1_TXCNT_IRQ
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int "Port 1 TX Interrupt Threshold Count"
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default 0
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depends on UART_SIFIVE_PORT_1
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help
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Port 1 TX Threshold at which the TX FIFO interrupt triggers.
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