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https://github.com/zephyrproject-rtos/zephyr
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39b2a09f38
Rewritten Xtensa CCOUNT driver along the lines of all the other new drivers. The new API permits much smaller code. Notably: The Xtensa counter is a 32 bit up-counter with a comparator register. It's in some sense the archetype of this kind of timer as it's the simplest of the bunch (everything else has quirks: NRF is very slow and 24 bit, HPET has a runtime frequency detection, RISC-V is 64 bit...). I should have written this one first. Note also that this includes a blacklist of the xtensa architecture on the tests/driver/ipm test. I'm getting spurious failures there where a k_sem_take() call with a non-zero timeout is being made out of the console output code in interrupt context. This seems to have nothing to do with the timer; I suspect it's because the old timer drivers would (incorrectly!) call z_clock_announce() in non-interrupt context in some contexts (e.g. "expiring really soon"). Apparently this test (or something in the IPM or Xtensa console code) was somehow relying on that on Xtensa. But IPM is a Quark thing and there's no particular reason to run this test there. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
256 lines
7.5 KiB
Plaintext
256 lines
7.5 KiB
Plaintext
# Kconfig - timer driver configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menu "Timer Drivers"
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config HPET_TIMER
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bool "HPET timer"
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depends on X86
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select IOAPIC
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select LOAPIC
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select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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select TICKLESS_CAPABLE
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help
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This option selects High Precision Event Timer (HPET) as a
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system timer.
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config HPET_TIMER_LEGACY_EMULATION
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bool "HPET timer legacy emulation mode"
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depends on HPET_TIMER
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help
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This option switches HPET to legacy emulation mode.
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In this mode 8254 PIT is disabled, HPET timer0 is connected
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to IOAPIC IRQ2, timer1 -- to IOAPIC IRQ8.
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config HPET_TIMER_DEBUG
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bool "Enable HPET debug output"
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depends on HPET_TIMER && PRINTK
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help
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This option enables HPET debugging output.
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config HPET_TIMER_BASE_ADDRESS
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hex "HPET Base Address"
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default 0xFED00000
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depends on HPET_TIMER
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help
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This options specifies the base address of the HPET timer device.
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config HPET_TIMER_IRQ
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int "HPET Timer IRQ"
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default 20
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depends on HPET_TIMER
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help
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This option specifies the IRQ used by the HPET timer.
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config HPET_TIMER_IRQ_PRIORITY
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int "HPET Timer IRQ Priority"
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default 4
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depends on HPET_TIMER
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help
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This option specifies the IRQ priority used by the HPET timer.
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choice
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depends on HPET_TIMER
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prompt "HPET Interrupt Trigger Condition"
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default HPET_TIMER_FALLING_EDGE
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config HPET_TIMER_FALLING_EDGE
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bool "Falling Edge"
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help
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This option signifies that the HPET timer uses falling edge interrupts.
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config HPET_TIMER_RISING_EDGE
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bool "Rising Edge"
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help
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This option signifies that the HPET timer uses rising edge interrupts.
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config HPET_TIMER_LEVEL_HIGH
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bool "Level High"
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help
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This option signifies that the HPET timer uses level high interrupts.
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config HPET_TIMER_LEVEL_LOW
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bool "Level Low"
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help
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This option signifies that the HPET timer uses level low interrupts.
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endchoice
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config LOAPIC_TIMER
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bool "LOAPIC timer"
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depends on (LOAPIC || MVIC) && X86
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help
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This option selects LOAPIC timer as a system timer.
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config LOAPIC_TIMER_IRQ
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int "Local APIC Timer IRQ"
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default 24
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depends on LOAPIC_TIMER
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help
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This option specifies the IRQ used by the LOAPIC timer.
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config LOAPIC_TIMER_IRQ_PRIORITY
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int "Local APIC Timer IRQ Priority"
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default 2
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depends on LOAPIC_TIMER
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help
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This options specifies the IRQ priority used by the LOAPIC timer.
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config TSC_CYCLES_PER_SEC
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int "Frequency of x86 CPU timestamp counter"
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default 0
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depends on LOAPIC_TIMER
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help
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The x86 implementation of LOAPIC k_cycle_get_32() relies on the x86 TSC.
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This runs at the CPU speed and not the bus speed. If set to 0, the
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value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC will be used instead;
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many MCUs these values are the same.
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config ARCV2_TIMER
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bool "ARC Timer"
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default y
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depends on ARC
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help
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This module implements a kernel device driver for the ARCv2 processor timer 0
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and provides the standard "system clock driver" interfaces.
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config ARCV2_TIMER_IRQ_PRIORITY
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int "ARC timer interrupt priority"
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default 0
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depends on ARCV2_TIMER
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help
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This option specifies the IRQ priority used by the ARC timer. Lower
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values have higher priority.
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config CORTEX_M_SYSTICK
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bool "Cortex-M SYSTICK timer"
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default y
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depends on CPU_HAS_SYSTICK
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Cortex-M processor
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SYSTICK timer and provides the standard "system clock driver" interfaces.
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config ALTERA_AVALON_TIMER
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bool "Altera Avalon Interval Timer"
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default y
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depends on NIOS2
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help
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This module implements a kernel device driver for the Altera Avalon
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Interval Timer as described in the Embedded IP documentation, for use
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with Nios II and possibly other Altera soft CPUs. It provides the
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standard "system clock driver" interfaces.
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config NRF_RTC_TIMER
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bool "nRF Real Time Counter (NRF_RTC1) Timer"
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default y
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depends on CLOCK_CONTROL_NRF5
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the nRF Real Time
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Counter NRF_RTC1 and provides the standard "system clock driver"
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interfaces.
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config PULPINO_TIMER
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bool "pulpino Timer"
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default y
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depends on SOC_RISCV32_PULPINO
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help
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This module implements a kernel device driver for the pulpino processor
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timer driver. It provides the standard "system clock driver" interfaces.
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config RISCV_MACHINE_TIMER
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bool "RISCV Machine Timer"
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depends on SOC_FAMILY_RISCV_PRIVILEGE
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the generic RISCV machine
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timer driver. It provides the standard "system clock driver" interfaces.
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config NATIVE_POSIX_TIMER
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bool "(POSIX) native_posix timer driver"
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default y
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depends on BOARD_NATIVE_POSIX
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help
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This module implements a kernel device driver for the native_posix HW timer
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model
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config XTENSA_TIMER
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bool "Xtensa timer support"
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depends on XTENSA
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default y
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select TICKLESS_CAPABLE
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help
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Enables a system timer driver for Xtensa based on the CCOUNT
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and CCOMPARE special registers.
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config XTENSA_TIMER_ID
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int "System timer CCOMPAREn register index"
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default 1
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depends on XTENSA_TIMER
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help
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Index of the CCOMPARE register (and associated interrupt)
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used for the system timer. Xtensa CPUs have hard-configured
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interrupt priorities associated with each timer, and some of
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them can be unmaskable (and thus not usable by OS code that
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need synchronization, like the timer subsystem!). Choose
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carefully. Generally you want the timer with the highest
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priority maskable interrupt.
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config SYSTEM_CLOCK_DISABLE
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bool "API to disable system clock"
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help
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This option enables the sys_clock_disable() API in the kernel. It is
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needed by some subsystems (which will automatically select it), but is
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rarely needed by applications.
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config TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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bool "Timer queries its hardware to find its frequency at runtime"
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help
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The drivers select this option automatically when needed. Do not modify
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this unless you have a very good reason for it.
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config SYSTEM_CLOCK_INIT_PRIORITY
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int "System clock driver initialization priority"
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default 0
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help
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This options can be used to set a specific initialization priority
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value for the system clock driver. As driver initialization might need
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the clock to be running already, you should let the default value as it
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is (0).
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config TICKLESS_CAPABLE
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bool "Timer driver supports tickless operation"
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help
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Timer drivers should select this flag if they are capable of
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supporting tickless operation. That is, a call to
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z_clock_set_timeout() with a number of ticks greater than
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one should be expected not to produce a call to
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z_clock_announce() (really, not to produce an interrupt at
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all) until the specified expiration.
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config QEMU_TICKLESS_WORKAROUND
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bool "Disable tickless on qemu due to asynchrony bug"
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depends on QEMU_TARGET && TICKLESS_KERNEL
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help
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Qemu (without -icount) has trouble keeping time when the
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host process needs to timeshare. The host OS will routinely
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schedule out a process at timescales equivalent to the guest
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tick rate. With traditional ticks delivered regularly by
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the hardware, that's mostly OK as it looks like a late
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interrupt. But in tickless mode, the driver needs some CPU
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in order to schedule the tick in the first place. If that
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gets delayed across a tick boundary, time gets wonky. This
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tunable is a hint to the driver to disable tickless
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accounting on qemu. Use it only on tests that are known to
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have problems.
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endmenu
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