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84d90e456a
The device Multi-Input Wake-Up Unit (MIWU) supports the embedded controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows chip has better power consumption. Also, it provides signal conditioning such as 'Level' and 'Edge' trigger type and grouping of external interrupt sources of NVIC. The NPCX series has three identical MIWU modules: MIWU0, MIWU1, MIWU2. Together, they support a total of over 140 internal and/or external wake-up sources. In this CL, we use device tree files to present the relationship bewteen MIWU and the other devices in different npcx series. For npcx7 series, it include: 1. npcx7-miwus-int-map.dtsi: it presents relationship between MIWU group and NVIC interrupt in npcx7. Please notice it isn't 1-to-1 mapping. 2. npcx7-miwus-wui-map.dtsi: it presents relationship between input of MIWU and its source device such as gpio, timer, eSPI VWs and so on. This CL also includes: 1. Add MIWU device tree declarations. 2. MIWU api function declarations and implementation to configure signal conditions and callback function mechanism. They can be be classified into two types. One is for GPIO which connects original gpio callback implemetation and the other is for generic devices such as timer, eSPI, and so on. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
# interrupt controller configuration options
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# Copyright (c) 2015 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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menu "Interrupt Controllers"
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config ARCV2_INTERRUPT_UNIT
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bool "ARCv2 Interrupt Unit"
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default y
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depends on ARC
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help
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The ARCv2 interrupt unit has 16 allocated exceptions associated with
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vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
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The interrupt unit is optional in the ARCv2-based processors. When
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building a processor, you can configure the processor to include an
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interrupt unit. The ARCv2 interrupt unit is highly programmable.
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config PLIC
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bool "Platform Level Interrupt Controller (PLIC)"
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default y
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depends on SOC_FAMILY_RISCV_PRIVILEGE
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select RISCV_HAS_PLIC
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select MULTI_LEVEL_INTERRUPTS
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select 2ND_LEVEL_INTERRUPTS
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help
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Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the RISC-V SoC;
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config SWERV_PIC
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bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
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default n
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help
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Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;
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config VEXRISCV_LITEX_IRQ
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bool "VexRiscv LiteX Interrupt controller"
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depends on SOC_RISCV32_LITEX_VEXRISCV
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help
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IRQ implementation for LiteX VexRiscv
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source "drivers/interrupt_controller/Kconfig.multilevel"
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source "drivers/interrupt_controller/Kconfig.loapic"
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source "drivers/interrupt_controller/Kconfig.dw"
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source "drivers/interrupt_controller/Kconfig.stm32"
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source "drivers/interrupt_controller/Kconfig.cavs"
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source "drivers/interrupt_controller/Kconfig.rv32m1"
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source "drivers/interrupt_controller/Kconfig.sam0"
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source "drivers/interrupt_controller/Kconfig.gic"
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source "drivers/interrupt_controller/Kconfig.npcx"
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endmenu
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