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https://github.com/zephyrproject-rtos/zephyr
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5100850767
This PR adds support for BQ32002 RTC chip. Supported functionalities: * Time setting/reading * Alarm setting/reading * Calibration setting/reading * IRQ frequency configuration Tested on nRF52833-DK board. Signed-off-by: Marcin Lyda <elektromarcin@gmail.com>
373 lines
10 KiB
C
373 lines
10 KiB
C
/*
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* Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/rtc.h>
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#include "rtc_utils.h"
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LOG_MODULE_REGISTER(bq32002, CONFIG_RTC_LOG_LEVEL);
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#define DT_DRV_COMPAT ti_bq32002
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#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
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#warning "Texas Instruments BQ32002 RTC driver enabled without any devices"
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#endif
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/* Registers */
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#define BQ32002_SECONDS_REG 0x00
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#define BQ32002_MINUTES_REG 0x01
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#define BQ32002_CENT_HOURS_REG 0x02
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#define BQ32002_DAY_REG 0x03
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#define BQ32002_DATE_REG 0x04
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#define BQ32002_MONTH_REG 0x05
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#define BQ32002_YEARS_REG 0x06
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#define BQ32002_CAL_CFG1_REG 0x07
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#define BQ32002_CFG2_REG 0x09
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#define BQ32002_SF_KEY_1_REG 0x20
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#define BQ32002_SF_KEY_2_REG 0x21
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#define BQ32002_SFR_REG 0x22
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/* Bitmasks */
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#define BQ32002_SECONDS_MASK GENMASK(6, 0)
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#define BQ32002_MINUTES_MASK GENMASK(6, 0)
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#define BQ32002_HOURS_MASK GENMASK(5, 0)
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#define BQ32002_DAY_MASK GENMASK(2, 0)
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#define BQ32002_DATE_MASK GENMASK(5, 0)
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#define BQ32002_MONTH_MASK GENMASK(4, 0)
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#define BQ32002_YEAR_MASK GENMASK(7, 0)
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#define BQ32002_CAL_MASK GENMASK(4, 0)
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#define BQ32002_OSC_STOP_MASK BIT(7)
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#define BQ32002_OSC_FAIL_MASK BIT(7)
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#define BQ32002_CENT_EN_MASK BIT(7)
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#define BQ32002_CENT_MASK BIT(6)
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#define BQ32002_OUT_MASK BIT(7)
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#define BQ32002_FREQ_TEST_MASK BIT(6)
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#define BQ32002_CAL_SIGN_MASK BIT(5)
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#define BQ32002_FTF_MASK BIT(0)
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/* Keys to unlock special function register */
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#define BQ32002_SF_KEY_1 0x5E
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#define BQ32002_SF_KEY_2 0xC7
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/* BQ32002 counts weekdays from 1 to 7 */
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#define BQ32002_DAY_OFFSET -1
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/* BQ32002 counts months from 1 to 12 */
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#define BQ32002_MONTH_OFFSET -1
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/* Year 2000 value represented as tm_year value */
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#define BQ32002_TM_YEAR_2000 (2000 - 1900)
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/* Calibration constants, see BQ32002 datasheet, Table 12, p.16 */
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#define BQ32002_CAL_PPB_PER_LSB_POS 2034 /* 1e9 / 491520 */
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#define BQ32002_CAL_PPB_PER_LSB_NEG 4069 /* 1e9 / 245760 */
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#define BQ32002_CAL_PPB_MIN (-31 * BQ32002_CAL_PPB_PER_LSB_POS)
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#define BQ32002_CAL_PPB_MAX (31 * BQ32002_CAL_PPB_PER_LSB_NEG)
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/* IRQ frequency property enum values */
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#define BQ32002_IRQ_FREQ_ENUM_1HZ 0
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#define BQ32002_IRQ_FREQ_ENUM_512HZ 1
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#define BQ32002_IRQ_FREQ_ENUM_DISABLED 2
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/* RTC time fields supported by BQ32002 */
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#define BQ32002_RTC_TIME_MASK \
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(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
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RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR | \
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RTC_ALARM_TIME_MASK_WEEKDAY)
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struct bq32002_config {
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struct i2c_dt_spec i2c;
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uint8_t irq_freq;
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};
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struct bq32002_data {
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struct k_sem lock;
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};
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static void bq32002_lock_sem(const struct device *dev)
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{
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struct bq32002_data *data = dev->data;
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(void)k_sem_take(&data->lock, K_FOREVER);
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}
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static void bq32002_unlock_sem(const struct device *dev)
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{
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struct bq32002_data *data = dev->data;
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k_sem_give(&data->lock);
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}
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static int bq32002_set_irq_frequency(const struct device *dev)
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{
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const struct bq32002_config *config = dev->config;
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uint8_t sf_regs[3];
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uint8_t cfg1_val;
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uint8_t cfg2_val;
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int err;
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switch (config->irq_freq) {
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case BQ32002_IRQ_FREQ_ENUM_1HZ:
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cfg1_val = BQ32002_FREQ_TEST_MASK;
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cfg2_val = BQ32002_FTF_MASK;
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break;
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case BQ32002_IRQ_FREQ_ENUM_512HZ:
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cfg1_val = BQ32002_FREQ_TEST_MASK;
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cfg2_val = 0;
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break;
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default:
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cfg1_val = BQ32002_OUT_MASK;
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cfg2_val = 0;
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break;
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}
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err = i2c_reg_update_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, BQ32002_FREQ_TEST_MASK,
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cfg1_val);
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if (err) {
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return err;
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}
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/* Update FTF value if frequency output enabled */
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if (cfg1_val & BQ32002_FREQ_TEST_MASK) {
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sf_regs[0] = BQ32002_SF_KEY_1;
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sf_regs[1] = BQ32002_SF_KEY_2;
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sf_regs[2] = cfg2_val;
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err = i2c_burst_write_dt(&config->i2c, BQ32002_SF_KEY_1_REG, sf_regs,
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sizeof(sf_regs));
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if (err) {
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return err;
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}
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}
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return 0;
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}
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static int bq32002_set_time(const struct device *dev, const struct rtc_time *timeptr)
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{
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const struct bq32002_config *config = dev->config;
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int err;
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uint8_t regs[7];
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if ((timeptr == NULL) || !rtc_utils_validate_rtc_time(timeptr, BQ32002_RTC_TIME_MASK)) {
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return -EINVAL;
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}
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bq32002_lock_sem(dev);
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/* Update the registers */
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regs[0] = bin2bcd(timeptr->tm_sec) & BQ32002_SECONDS_MASK;
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regs[1] = bin2bcd(timeptr->tm_min) & BQ32002_MINUTES_MASK; /* Clear oscillator fail flag */
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regs[2] = (bin2bcd(timeptr->tm_hour) & BQ32002_HOURS_MASK) | BQ32002_CENT_EN_MASK;
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regs[3] = bin2bcd(timeptr->tm_wday - BQ32002_DAY_OFFSET) & BQ32002_DAY_MASK;
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regs[4] = bin2bcd(timeptr->tm_mday) & BQ32002_DATE_MASK;
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regs[5] = bin2bcd(timeptr->tm_mon - BQ32002_MONTH_OFFSET) & BQ32002_MONTH_MASK;
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/* Determine which century we're in */
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if (timeptr->tm_year >= BQ32002_TM_YEAR_2000) {
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regs[2] |= BQ32002_CENT_MASK;
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regs[6] = bin2bcd(timeptr->tm_year - BQ32002_TM_YEAR_2000) & BQ32002_YEAR_MASK;
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} else {
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regs[6] = bin2bcd(timeptr->tm_year) & BQ32002_YEAR_MASK;
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}
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/* Write new time to the chip */
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err = i2c_burst_write_dt(&config->i2c, BQ32002_SECONDS_REG, regs, sizeof(regs));
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bq32002_unlock_sem(dev);
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if (!err) {
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LOG_DBG("Set time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
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"minute: %d, second: %d",
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timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
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timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
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}
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return err;
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}
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static int bq32002_get_time(const struct device *dev, struct rtc_time *timeptr)
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{
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const struct bq32002_config *config = dev->config;
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int err;
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uint8_t reg_val;
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uint8_t regs[7];
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if (timeptr == NULL) {
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return -EINVAL;
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}
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bq32002_lock_sem(dev);
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err = i2c_reg_read_byte_dt(&config->i2c, BQ32002_MINUTES_REG, ®_val);
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if (err) {
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goto out_unlock;
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}
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/* Oscillator failure detected, data might be invalid */
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if (reg_val & BQ32002_OSC_FAIL_MASK) {
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err = -ENODATA;
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goto out_unlock;
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}
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err = i2c_burst_read_dt(&config->i2c, BQ32002_SECONDS_REG, regs, sizeof(regs));
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if (err) {
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goto out_unlock;
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}
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timeptr->tm_sec = bcd2bin(regs[0] & BQ32002_SECONDS_MASK);
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timeptr->tm_min = bcd2bin(regs[1] & BQ32002_MINUTES_MASK);
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timeptr->tm_hour = bcd2bin(regs[2] & BQ32002_HOURS_MASK);
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timeptr->tm_wday = bcd2bin(regs[3] & BQ32002_DAY_MASK) + BQ32002_DAY_OFFSET;
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timeptr->tm_mday = bcd2bin(regs[4] & BQ32002_DATE_MASK);
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timeptr->tm_mon = bcd2bin(regs[5] & BQ32002_MONTH_MASK) + BQ32002_MONTH_OFFSET;
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timeptr->tm_year = bcd2bin(regs[6] & BQ32002_YEAR_MASK);
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timeptr->tm_yday = -1; /* Unsupported */
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timeptr->tm_isdst = -1; /* Unsupported */
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timeptr->tm_nsec = 0; /* Unsupported */
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/* Apply century offset */
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if (regs[2] & BQ32002_CENT_MASK) {
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timeptr->tm_year += BQ32002_TM_YEAR_2000;
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}
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out_unlock:
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bq32002_unlock_sem(dev);
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if (!err) {
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LOG_DBG("Read time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
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"minute: "
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"%d, second: %d",
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timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
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timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
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}
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return err;
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}
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#ifdef CONFIG_RTC_CALIBRATION
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static int bq32002_set_calibration(const struct device *dev, int32_t freq_ppb)
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{
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const struct bq32002_config *config = dev->config;
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int err;
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uint8_t offset;
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uint8_t reg_val;
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if ((freq_ppb < BQ32002_CAL_PPB_MIN) || (freq_ppb > BQ32002_CAL_PPB_MAX)) {
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LOG_ERR("Calibration value %d ppb out of range", freq_ppb);
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return -EINVAL;
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}
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err = i2c_reg_read_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, ®_val);
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if (err) {
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return err;
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}
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reg_val &= ~(BQ32002_CAL_SIGN_MASK | BQ32002_CAL_MASK);
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if (freq_ppb > 0) {
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reg_val |= BQ32002_CAL_SIGN_MASK; /* Negative sign speeds the oscillator up */
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offset =
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DIV_ROUND_CLOSEST(freq_ppb, BQ32002_CAL_PPB_PER_LSB_NEG) & BQ32002_CAL_MASK;
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} else {
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offset = DIV_ROUND_CLOSEST(-freq_ppb, BQ32002_CAL_PPB_PER_LSB_POS) &
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BQ32002_CAL_MASK;
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}
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reg_val |= offset;
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err = i2c_reg_write_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, reg_val);
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if (err) {
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return err;
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}
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LOG_DBG("Set calibration: frequency ppb: %d, offset value: %d, sign: %d", freq_ppb, offset,
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freq_ppb > 0);
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return 0;
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}
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static int bq32002_get_calibration(const struct device *dev, int32_t *freq_ppb)
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{
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const struct bq32002_config *config = dev->config;
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uint8_t reg_val;
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uint8_t offset;
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int err;
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err = i2c_reg_read_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, ®_val);
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if (err) {
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return err;
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}
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offset = reg_val & BQ32002_CAL_MASK;
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if (reg_val & BQ32002_CAL_SIGN_MASK) {
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*freq_ppb = offset * BQ32002_CAL_PPB_PER_LSB_NEG;
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} else {
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*freq_ppb = -offset * BQ32002_CAL_PPB_PER_LSB_POS;
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}
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LOG_DBG("Get calibration: frequency ppb: %d, offset value: %d, sign: %d", *freq_ppb, offset,
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*freq_ppb > 0);
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return 0;
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}
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#endif
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static DEVICE_API(rtc, bq32002_driver_api) = {
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.set_time = bq32002_set_time,
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.get_time = bq32002_get_time,
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#ifdef CONFIG_RTC_CALIBRATION
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.set_calibration = bq32002_set_calibration,
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.get_calibration = bq32002_get_calibration
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#endif
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};
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static int bq32002_init(const struct device *dev)
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{
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const struct bq32002_config *config = dev->config;
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struct bq32002_data *data = dev->data;
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int err;
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(void)k_sem_init(&data->lock, 1, 1);
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if (!i2c_is_ready_dt(&config->i2c)) {
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LOG_ERR("I2C bus not ready");
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return -ENODEV;
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}
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/* Start the oscillator */
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err = i2c_reg_update_byte_dt(&config->i2c, BQ32002_SECONDS_REG, BQ32002_OSC_STOP_MASK, 0);
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if (err) {
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return err;
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}
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/* Configure IRQ output frequency */
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err = bq32002_set_irq_frequency(dev);
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if (err) {
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return err;
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}
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return 0;
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}
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#define BQ32002_INIT(inst) \
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static struct bq32002_data bq32002_data_##inst; \
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static const struct bq32002_config bq32002_config_##inst = { \
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.i2c = I2C_DT_SPEC_INST_GET(inst), \
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.irq_freq = \
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DT_INST_ENUM_IDX_OR(inst, irq_frequency, BQ32002_IRQ_FREQ_ENUM_DISABLED) \
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}; \
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DEVICE_DT_INST_DEFINE(inst, &bq32002_init, NULL, &bq32002_data_##inst, \
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&bq32002_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, \
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&bq32002_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(BQ32002_INIT)
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