mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-05 01:42:29 +00:00
84c9db39e7
Using AON for GPIO kconfigs is very specifc to quark se, there is no need to make this special for this platform. Use the existing scheme instead. Change-Id: I946431490380dc0f537d6056277a94c9c9c80fed Signed-off-by: Anas Nashif <anas.nashif@intel.com>
486 lines
13 KiB
C
486 lines
13 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/ioapic.h>
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#include <gpio.h>
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#include <init.h>
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#include <nanokernel.h>
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#include <sys_io.h>
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#include "qm_gpio.h"
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#include "gpio_utils.h"
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#include "qm_isr.h"
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#include "clk.h"
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#include <power.h>
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struct gpio_qmsi_config {
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qm_gpio_t gpio;
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uint8_t num_pins;
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};
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struct gpio_qmsi_runtime {
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sys_slist_t callbacks;
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uint32_t pin_callbacks;
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#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
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struct nano_sem sem;
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#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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uint32_t device_power_state;
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#endif
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};
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#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
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#define RP_GET(dev) (&((struct gpio_qmsi_runtime *)(dev->driver_data))->sem)
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static const int reentrancy_protection = 1;
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#else
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#define RP_GET(context) (NULL)
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static const int reentrancy_protection;
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#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
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static void gpio_reentrancy_init(struct device *dev)
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{
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if (!reentrancy_protection) {
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return;
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}
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nano_sem_init(RP_GET(dev));
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nano_sem_give(RP_GET(dev));
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}
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static void gpio_critical_region_start(struct device *dev)
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{
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if (!reentrancy_protection) {
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return;
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}
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nano_sem_take(RP_GET(dev), TICKS_UNLIMITED);
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}
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static void gpio_critical_region_end(struct device *dev)
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{
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if (!reentrancy_protection) {
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return;
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}
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nano_sem_give(RP_GET(dev));
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}
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int gpio_qmsi_init(struct device *dev);
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void gpio_qmsi_set_power_state(struct device *dev, uint32_t power_state)
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{
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struct gpio_qmsi_runtime *context = dev->driver_data;
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context->device_power_state = power_state;
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}
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static uint32_t gpio_qmsi_get_power_state(struct device *dev)
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{
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struct gpio_qmsi_runtime *context = dev->driver_data;
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return context->device_power_state;
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}
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#else
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#define gpio_qmsi_set_power_state(...)
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#endif
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#ifdef CONFIG_GPIO_QMSI_0
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static struct gpio_qmsi_config gpio_0_config = {
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.gpio = QM_GPIO_0,
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.num_pins = QM_NUM_GPIO_PINS,
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};
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static struct gpio_qmsi_runtime gpio_0_runtime;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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QM_RW uint32_t save_reg[10];
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static uint32_t int_gpio_mask_save;
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static int gpio_suspend_device(struct device *dev)
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{
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int_gpio_mask_save = REG_VAL(&QM_SCSS_INT->int_gpio_mask);
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save_reg[0] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_swporta_dr);
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save_reg[1] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_swporta_ddr);
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save_reg[2] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_swporta_ctl);
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save_reg[3] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_inten);
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save_reg[4] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_intmask);
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save_reg[5] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_inttype_level);
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save_reg[6] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_int_polarity);
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save_reg[7] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_debounce);
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save_reg[8] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_ls_sync);
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save_reg[9] = REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_int_bothedge);
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gpio_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int gpio_resume_device_from_suspend(struct device *dev)
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{
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_swporta_dr) = save_reg[0];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_swporta_ddr) = save_reg[1];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_swporta_ctl) = save_reg[2];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_inten) = save_reg[3];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_intmask) = save_reg[4];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_inttype_level) = save_reg[5];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_int_polarity) = save_reg[6];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_debounce) = save_reg[7];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_ls_sync) = save_reg[8];
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REG_VAL(&QM_GPIO[QM_GPIO_0]->gpio_int_bothedge) = save_reg[9];
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REG_VAL(&QM_SCSS_INT->int_gpio_mask) = int_gpio_mask_save;
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gpio_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int gpio_qmsi_device_ctrl(struct device *port, uint32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return gpio_suspend_device(port);
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} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return gpio_resume_device_from_suspend(port);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((uint32_t *)context) = gpio_qmsi_get_power_state(port);
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return 0;
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}
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return 0;
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}
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#endif
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DEVICE_DEFINE(gpio_0, CONFIG_GPIO_QMSI_0_NAME, &gpio_qmsi_init,
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gpio_qmsi_device_ctrl, &gpio_0_runtime, &gpio_0_config,
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SECONDARY, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
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#endif /* CONFIG_GPIO_QMSI_0 */
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#ifdef CONFIG_GPIO_QMSI_1
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static struct gpio_qmsi_config gpio_aon_config = {
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.gpio = QM_AON_GPIO_0,
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.num_pins = QM_NUM_AON_GPIO_PINS,
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};
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static struct gpio_qmsi_runtime gpio_aon_runtime;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static uint32_t int_gpio_aon_mask_save;
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static int gpio_aon_suspend_device(struct device *dev)
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{
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int_gpio_aon_mask_save = REG_VAL(&QM_SCSS_INT->int_aon_gpio_mask);
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gpio_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int gpio_aon_resume_device_from_suspend(struct device *dev)
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{
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REG_VAL(&QM_SCSS_INT->int_aon_gpio_mask) = int_gpio_aon_mask_save;
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gpio_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int gpio_aon_device_ctrl(struct device *port, uint32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return gpio_aon_suspend_device(port);
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} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return gpio_aon_resume_device_from_suspend(port);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((uint32_t *)context) = gpio_qmsi_get_power_state(port);
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return 0;
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}
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return 0;
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}
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#endif
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DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_1_NAME, &gpio_qmsi_init,
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gpio_aon_device_ctrl, &gpio_aon_runtime, &gpio_aon_config,
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SECONDARY, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
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#endif /* CONFIG_GPIO_QMSI_1 */
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/*
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* TODO: Zephyr's API is not clear about the behavior of the this
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* application callback. This topic is currently under
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* discussion, so this implementation will be fixed as soon as a
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* decision is made.
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*/
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static void gpio_qmsi_callback(struct device *port, uint32_t status)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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const uint32_t enabled_mask = context->pin_callbacks & status;
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if (enabled_mask) {
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_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
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}
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}
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static void gpio_qmsi_0_int_callback(void *data, uint32_t status)
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{
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#ifndef CONFIG_GPIO_QMSI_0
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return;
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#else
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struct device *port = DEVICE_GET(gpio_0);
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gpio_qmsi_callback(port, status);
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#endif
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}
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#ifdef CONFIG_GPIO_QMSI_1
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static void gpio_qmsi_aon_int_callback(void *data, uint32_t status)
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{
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struct device *port = DEVICE_GET(gpio_aon);
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gpio_qmsi_callback(port, status);
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}
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#endif /* CONFIG_GPIO_QMSI_1 */
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static void qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
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{
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if (value) {
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sys_set_bit((uintptr_t) target, bit);
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} else {
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sys_clear_bit((uintptr_t) target, bit);
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}
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}
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static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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/* Save int mask and mask this pin while we configure the port.
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* We do this to avoid "spurious interrupts", which is a behavior
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* we have observed on QMSI and that still needs investigation.
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*/
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qm_gpio_port_config_t cfg = { 0 };
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cfg.direction = QM_GPIO[gpio]->gpio_swporta_ddr;
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cfg.int_en = QM_GPIO[gpio]->gpio_inten;
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cfg.int_type = QM_GPIO[gpio]->gpio_inttype_level;
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cfg.int_polarity = QM_GPIO[gpio]->gpio_int_polarity;
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cfg.int_debounce = QM_GPIO[gpio]->gpio_debounce;
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cfg.int_bothedge = QM_GPIO[gpio]->gpio_int_bothedge;
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qmsi_write_bit(&cfg.direction, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT) {
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qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE));
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qmsi_write_bit(&cfg.int_polarity, pin,
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(flags & GPIO_INT_ACTIVE_HIGH));
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qmsi_write_bit(&cfg.int_debounce, pin,
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(flags & GPIO_INT_DEBOUNCE));
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qmsi_write_bit(&cfg.int_bothedge, pin,
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(flags & GPIO_INT_DOUBLE_EDGE));
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qmsi_write_bit(&cfg.int_en, pin, 1);
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}
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switch (gpio) {
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case QM_GPIO_0:
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cfg.callback = gpio_qmsi_0_int_callback;
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break;
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#ifdef CONFIG_GPIO_QMSI_1
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case QM_AON_GPIO_0:
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cfg.callback = gpio_qmsi_aon_int_callback;
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break;
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#endif /* CONFIG_GPIO_QMSI_1 */
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default:
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return;
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}
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gpio_critical_region_start(port);
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qm_gpio_set_config(gpio, &cfg);
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gpio_critical_region_end(port);
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}
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static inline void qmsi_port_config(struct device *port, int flags)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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uint8_t num_pins = gpio_config->num_pins;
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int i;
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for (i = 0; i < num_pins; i++) {
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qmsi_pin_config(port, i, flags);
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}
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}
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static inline int gpio_qmsi_config(struct device *port,
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int access_op, uint32_t pin, int flags)
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{
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return -EINVAL;
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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qmsi_pin_config(port, pin, flags);
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} else {
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qmsi_port_config(port, flags);
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}
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return 0;
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}
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static inline int gpio_qmsi_write(struct device *port,
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int access_op, uint32_t pin, uint32_t value)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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gpio_critical_region_start(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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qm_gpio_set_pin(gpio, pin);
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} else {
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qm_gpio_clear_pin(gpio, pin);
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}
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} else {
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qm_gpio_write_port(gpio, value);
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}
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gpio_critical_region_end(port);
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return 0;
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}
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static inline int gpio_qmsi_read(struct device *port,
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int access_op, uint32_t pin, uint32_t *value)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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qm_gpio_t gpio = gpio_config->gpio;
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qm_gpio_state_t state;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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qm_gpio_read_pin(gpio, pin, &state);
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*value = state;
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} else {
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qm_gpio_read_port(gpio, (uint32_t *const) value);
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}
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return 0;
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}
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static inline int gpio_qmsi_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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_gpio_manage_callback(&context->callbacks, callback, set);
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return 0;
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}
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static inline int gpio_qmsi_enable_callback(struct device *port,
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int access_op, uint32_t pin)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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gpio_critical_region_start(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks |= BIT(pin);
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} else {
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context->pin_callbacks = 0xffffffff;
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}
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gpio_critical_region_end(port);
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return 0;
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}
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static inline int gpio_qmsi_disable_callback(struct device *port,
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int access_op, uint32_t pin)
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{
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struct gpio_qmsi_runtime *context = port->driver_data;
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gpio_critical_region_start(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks &= ~BIT(pin);
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} else {
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context->pin_callbacks = 0;
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}
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gpio_critical_region_end(port);
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return 0;
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}
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static struct gpio_driver_api api_funcs = {
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.config = gpio_qmsi_config,
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.write = gpio_qmsi_write,
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.read = gpio_qmsi_read,
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.manage_callback = gpio_qmsi_manage_callback,
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.enable_callback = gpio_qmsi_enable_callback,
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.disable_callback = gpio_qmsi_disable_callback,
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};
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int gpio_qmsi_init(struct device *port)
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{
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const struct gpio_qmsi_config *gpio_config = port->config->config_info;
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gpio_reentrancy_init(port);
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switch (gpio_config->gpio) {
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case QM_GPIO_0:
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clk_periph_enable(CLK_PERIPH_GPIO_REGISTER |
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CLK_PERIPH_GPIO_INTERRUPT |
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CLK_PERIPH_GPIO_DB |
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CLK_PERIPH_CLK);
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IRQ_CONNECT(QM_IRQ_GPIO_0, CONFIG_GPIO_QMSI_0_IRQ_PRI,
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qm_gpio_isr_0, 0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(QM_IRQ_GPIO_0);
|
|
QM_SCSS_INT->int_gpio_mask &= ~BIT(0);
|
|
break;
|
|
#ifdef CONFIG_GPIO_QMSI_1
|
|
case QM_AON_GPIO_0:
|
|
IRQ_CONNECT(QM_IRQ_AONGPIO_0,
|
|
CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_isr_0,
|
|
0, IOAPIC_LEVEL | IOAPIC_HIGH);
|
|
irq_enable(QM_IRQ_AONGPIO_0);
|
|
QM_SCSS_INT->int_aon_gpio_mask &= ~BIT(0);
|
|
break;
|
|
#endif /* CONFIG_GPIO_QMSI_1 */
|
|
default:
|
|
return -EIO;
|
|
}
|
|
|
|
gpio_qmsi_set_power_state(port, DEVICE_PM_ACTIVE_STATE);
|
|
|
|
port->driver_api = &api_funcs;
|
|
return 0;
|
|
}
|