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In npcx7 series, all of them support the Intel Enhanced Serial Peripheral Interface (eSPI) Revision 1.0. This specification provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. In addition to Host communication via the peripheral channel, it provides virtual wires support, out-of-band communication, and device mastering option over the Chipset SPI flash. Becisdes introducing eSPI device in npcx7, this CL also includes: 1. Add eSPI device tree declarations. 2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI Virtual-Wire signals, eSPI registers, and wake-up input sources. 3. Zephyr eSPI api implementation. 4, Add OOB (Out of Band tunneled SMBus) support. 5. Add configuration files for eSPI test suites. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
32 lines
672 B
Plaintext
32 lines
672 B
Plaintext
# NPCX eSPI driver configuration options
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# Copyright (c) 2020 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config ESPI_NPCX
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bool "Nuvoton NPCX embedd controller (EC) ESPI driver"
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depends on SOC_FAMILY_NPCX
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help
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This option enables the Intel Enhanced Serial Peripheral Interface
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(eSPI) for NPCX family of processors.
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# The default value 'y' for the existing options if ESPI_NPCX is selected.
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if ESPI_NPCX
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config ESPI_OOB_CHANNEL
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default y
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config ESPI_PERIPHERAL_8042_KBC
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default y
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config ESPI_PERIPHERAL_HOST_IO
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default y
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config ESPI_PERIPHERAL_DEBUG_PORT_80
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default y
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config ESPI_PERIPHERAL_UART
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default y
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endif #ESPI_NPCX
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