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https://github.com/zephyrproject-rtos/zephyr
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87e5493167
This driver is inspired from the w25qxxdv SPI NOR flash driver which was already implementing the CFI (Common Flash Interface) for its purpose. To handle other NOR flash a flash id table (as Linux do) which contains the geometry for a few SPI NOR flash based on their JEDEC ID has been introduced. We currently support the following flash: - W25Q80 - W25Q16 - W25Q32 - S25FL216K - MX25UM512 The read and write functions are able to handle more then one page at a time and return the number of bytes read or write. Also because every NOR flash expect to disable the write protection before writing or erasing, the write enable command is now part of the write and erase functions. Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
/*
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* Copyright (c) 2018 Savoir-Faire Linux.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_NOR_H__
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#define __SPI_NOR_H__
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#include <misc/util.h>
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#define SPI_NOR_MAX_ID_LEN 3
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struct spi_nor_config {
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u8_t id[SPI_NOR_MAX_ID_LEN];
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u32_t page_size;
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u32_t sector_size;
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u32_t n_sectors;
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u32_t block_size;
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u32_t flag;
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};
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/* Status register bits */
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#define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
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#define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */
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/* Flash opcodes */
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#define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
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#define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
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#define SPI_NOR_CMD_READ 0x03 /* Read data */
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#define SPI_NOR_CMD_WREN 0x06 /* Write enable */
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#define SPI_NOR_CMD_WRDI 0x04 /* Write disable */
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#define SPI_NOR_CMD_PP 0x02 /* Page program */
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#define SPI_NOR_CMD_SE 0x20 /* Sector erase */
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#define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */
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#define SPI_NOR_CMD_BE 0xD8 /* Block erase */
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#define SPI_NOR_CMD_CE 0xC7 /* Chip erase */
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#define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */
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#endif /*__SPI_NOR_H__*/
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