Andrew Boie 50d72ed9c9 x86: implement eager FP save/restore ... Speculative execution side channel attacks can read the entire FPU/SIMD register state on affected Intel Core processors, see CVE-2018-3665. We now have two options for managing floating point context between threads on x86: CONFIG_EAGER_FP_SHARING and CONFIG_LAZY_FP_SHARING. The mitigation is to unconditionally save/restore these registers on context switch, instead of the lazy sharing algorithm used by CONFIG_LAZY_FP_SHARING. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2019-03-11 20:36:55 -07:00
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offsets	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
cache_s.S
cache.c
CMakeLists.txt	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
cpuhalt.c
crt0.S
excstub.S	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
fatal.c
float.c	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
intstub.S	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
irq_manage.c
irq_offload.c
Kconfig
reboot_rst_cnt.c
spec_ctrl.c
swap.S	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
sys_fatal_error_handler.c
thread.c	x86: implement eager FP save/restore	2019-03-11 20:36:55 -07:00
userspace.S
x86_mmu.c