mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-27 18:55:22 +00:00
279cc2e448
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file configuration macros for riscv SOCs supporting the riscv
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* privileged architecture specification
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*/
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#ifndef __SOC_COMMON_H_
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#define __SOC_COMMON_H_
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/* IRQ numbers */
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#define RISCV_MACHINE_SOFT_IRQ 3 /* Machine Software Interrupt */
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#define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
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#define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
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#define RISCV_MAX_GENERIC_IRQ 11 /* Max Generic Interrupt */
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/* Exception numbers */
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#define RISCV_MACHINE_ECALL_EXP 11 /* Machine ECALL instruction */
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/*
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* SOC-specific MSTATUS related info
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*/
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/* MSTATUS register to save/restore upon interrupt/exception/context switch */
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#define SOC_MSTATUS_REG mstatus
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#define SOC_MSTATUS_IEN (1 << 3) /* Machine Interrupt Enable bit */
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/* Previous Privilege Mode - Machine Mode */
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#define SOC_MSTATUS_MPP_M_MODE (3 << 11)
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/* Interrupt Enable Bit in Previous Privilege Mode */
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#define SOC_MSTATUS_MPIE (1 << 7)
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/*
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* Default MSTATUS register value to restore from stack
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* upon scheduling a thread for the first time
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*/
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#define SOC_MSTATUS_DEF_RESTORE (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE)
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/* SOC-specific MCAUSE bitfields */
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/* Interrupt Mask */
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#define SOC_MCAUSE_IRQ_MASK (1 << 31)
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/* Exception code Mask */
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#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
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/* ECALL exception number */
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#define SOC_MCAUSE_ECALL_EXP RISCV_MACHINE_ECALL_EXP
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/* SOC-Specific EXIT ISR command */
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#define SOC_ERET mret
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#ifndef _ASMLANGUAGE
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void);
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#endif
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#if defined(CONFIG_RISCV_HAS_PLIC)
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void riscv_plic_irq_enable(u32_t irq);
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void riscv_plic_irq_disable(u32_t irq);
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int riscv_plic_irq_is_enabled(u32_t irq);
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void riscv_plic_set_priority(u32_t irq, u32_t priority);
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int riscv_plic_get_irq(void);
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#endif
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#endif /* !_ASMLANGUAGE */
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#endif /* __SOC_COMMON_H_ */
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