mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 00:31:57 +00:00
4344e27c26
Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
78 lines
1.5 KiB
C
78 lines
1.5 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief interrupt management code for riscv SOCs supporting the riscv
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privileged architecture specification
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*/
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#include <irq.h>
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void z_arch_irq_enable(unsigned int irq)
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{
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u32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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if (irq > RISCV_MAX_GENERIC_IRQ) {
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riscv_plic_irq_enable(irq);
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return;
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}
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#endif
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/*
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* CSR mie register is updated using atomic instruction csrrs
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* (atomic read and set bits in CSR register)
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*/
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__asm__ volatile ("csrrs %0, mie, %1\n"
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: "=r" (mie)
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: "r" (1 << irq));
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}
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void z_arch_irq_disable(unsigned int irq)
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{
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u32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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if (irq > RISCV_MAX_GENERIC_IRQ) {
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riscv_plic_irq_disable(irq);
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return;
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}
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#endif
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/*
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* Use atomic instruction csrrc to disable device interrupt in mie CSR.
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* (atomic read and clear bits in CSR register)
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*/
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__asm__ volatile ("csrrc %0, mie, %1\n"
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: "=r" (mie)
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: "r" (1 << irq));
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};
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int z_arch_irq_is_enabled(unsigned int irq)
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{
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u32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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if (irq > RISCV_MAX_GENERIC_IRQ)
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return riscv_plic_irq_is_enabled(irq);
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#endif
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__asm__ volatile ("csrr %0, mie" : "=r" (mie));
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return !!(mie & (1 << irq));
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}
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void)
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{
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/* ensure that all interrupts are disabled */
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(void)irq_lock();
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__asm__ volatile ("csrwi mie, 0\n"
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"csrwi mip, 0\n");
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}
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#endif
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