mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-12 08:05:58 +00:00
c7875b75aa
This patch adds I2C Slave support conforming to the syscalls and funcs, only for the STM32 V2 I2C Driver for the moment. It is capable of handling multi-master bus setups. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
612 lines
13 KiB
C
612 lines
13 KiB
C
/*
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* Copyright (c) 2016 BayLibre, SAS
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* Copyright (c) 2017 Linaro Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0 and STM32L4
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*
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*/
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#include <clock_control/stm32_clock_control.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <kernel.h>
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#include <board.h>
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#include <errno.h>
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#include <i2c.h>
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#include "i2c-priv.h"
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#include "i2c_ll_stm32.h"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_I2C_LEVEL
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#include <logging/sys_log.h>
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static inline void msg_init(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, u16_t slave,
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uint32_t transfer)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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if (LL_I2C_IsEnabledReloadMode(i2c)) {
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LL_I2C_SetTransferSize(i2c, msg->len);
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} else {
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if (I2C_ADDR_10_BITS & data->dev_config) {
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LL_I2C_SetMasterAddressingMode(i2c,
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LL_I2C_ADDRESSING_MODE_10BIT);
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LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave);
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} else {
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LL_I2C_SetMasterAddressingMode(i2c,
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LL_I2C_ADDRESSING_MODE_7BIT);
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LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave << 1);
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}
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if (!(msg->flags & I2C_MSG_STOP) && next_msg_flags &&
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!(*next_msg_flags & I2C_MSG_RESTART)) {
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LL_I2C_EnableReloadMode(i2c);
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} else {
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LL_I2C_DisableReloadMode(i2c);
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}
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LL_I2C_DisableAutoEndMode(i2c);
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LL_I2C_SetTransferRequest(i2c, transfer);
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LL_I2C_SetTransferSize(i2c, msg->len);
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#if defined(CONFIG_I2C_SLAVE)
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data->master_active = true;
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#endif
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LL_I2C_Enable(i2c);
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LL_I2C_GenerateStartCondition(i2c);
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}
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}
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void stm32_i2c_disable_transfer_interrupts(struct device *dev)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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LL_I2C_DisableIT_TX(i2c);
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LL_I2C_DisableIT_RX(i2c);
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LL_I2C_DisableIT_STOP(i2c);
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LL_I2C_DisableIT_NACK(i2c);
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LL_I2C_DisableIT_TC(i2c);
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LL_I2C_DisableIT_ERR(i2c);
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}
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static void stm32_i2c_enable_transfer_interrupts(struct device *dev)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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LL_I2C_EnableIT_STOP(i2c);
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LL_I2C_EnableIT_NACK(i2c);
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LL_I2C_EnableIT_TC(i2c);
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LL_I2C_EnableIT_ERR(i2c);
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}
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static void stm32_i2c_master_mode_end(struct device *dev)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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stm32_i2c_disable_transfer_interrupts(dev);
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#if defined(CONFIG_I2C_SLAVE)
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data->master_active = false;
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if (!data->slave_attached) {
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LL_I2C_Disable(i2c);
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}
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#else
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LL_I2C_Disable(i2c);
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#endif
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k_sem_give(&data->device_sync_sem);
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}
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#if defined(CONFIG_I2C_SLAVE)
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static void stm32_i2c_slave_event(struct device *dev)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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const struct i2c_slave_callbacks *slave_cb =
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data->slave_cfg->callbacks;
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if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
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u8_t val;
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slave_cb->read_processed(data->slave_cfg, &val);
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LL_I2C_TransmitData8(i2c, val);
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return;
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}
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if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
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u8_t val = LL_I2C_ReceiveData8(i2c);
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if (slave_cb->write_received(data->slave_cfg, val)) {
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
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}
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return;
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}
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if (LL_I2C_IsActiveFlag_NACK(i2c)) {
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LL_I2C_ClearFlag_NACK(i2c);
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}
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if (LL_I2C_IsActiveFlag_STOP(i2c)) {
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stm32_i2c_disable_transfer_interrupts(dev);
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/* Flush remaining TX byte before clearing Stop Flag */
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LL_I2C_ClearFlag_TXE(i2c);
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LL_I2C_ClearFlag_STOP(i2c);
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slave_cb->stop(data->slave_cfg);
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/* Prepare to ACK next transmissions address byte */
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
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}
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if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
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u32_t dir;
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LL_I2C_ClearFlag_ADDR(i2c);
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dir = LL_I2C_GetTransferDirection(i2c);
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if (dir == LL_I2C_DIRECTION_WRITE) {
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slave_cb->write_requested(data->slave_cfg);
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LL_I2C_EnableIT_RX(i2c);
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} else {
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u8_t val;
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slave_cb->read_requested(data->slave_cfg, &val);
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LL_I2C_TransmitData8(i2c, val);
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LL_I2C_EnableIT_TX(i2c);
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}
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stm32_i2c_enable_transfer_interrupts(dev);
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}
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}
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/* Attach and start I2C as slave */
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int i2c_stm32_slave_register(struct device *dev,
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struct i2c_slave_config *config)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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u32_t bitrate_cfg;
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int ret;
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if (!config) {
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return -EINVAL;
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}
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if (data->slave_attached) {
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return -EBUSY;
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}
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if (data->master_active) {
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return -EBUSY;
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}
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bitrate_cfg = _i2c_map_dt_bitrate(cfg->bitrate);
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ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
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if (ret < 0) {
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SYS_LOG_ERR("i2c: failure initializing");
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return ret;
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}
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data->slave_cfg = config;
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LL_I2C_Enable(i2c);
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LL_I2C_SetOwnAddress1(i2c, config->address << 1,
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LL_I2C_OWNADDRESS1_7BIT);
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LL_I2C_EnableOwnAddress1(i2c);
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data->slave_attached = true;
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SYS_LOG_DBG("i2c: slave registered");
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LL_I2C_EnableIT_ADDR(i2c);
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return 0;
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}
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int i2c_stm32_slave_unregister(struct device *dev,
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struct i2c_slave_config *config)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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if (!data->slave_attached) {
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return -EINVAL;
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}
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if (data->master_active) {
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return -EBUSY;
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}
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LL_I2C_DisableOwnAddress1(i2c);
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LL_I2C_DisableIT_ADDR(i2c);
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stm32_i2c_disable_transfer_interrupts(dev);
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LL_I2C_ClearFlag_NACK(i2c);
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LL_I2C_ClearFlag_STOP(i2c);
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LL_I2C_ClearFlag_ADDR(i2c);
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LL_I2C_Disable(i2c);
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SYS_LOG_DBG("i2c: slave unregistered");
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return 0;
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}
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#endif /* defined(CONFIG_I2C_SLAVE) */
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static void stm32_i2c_event(struct device *dev)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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#if defined(CONFIG_I2C_SLAVE)
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if (data->slave_attached && !data->master_active) {
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stm32_i2c_slave_event(dev);
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return;
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}
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#endif
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if (data->current.len) {
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/* Send next byte */
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if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
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LL_I2C_TransmitData8(i2c, *data->current.buf);
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}
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/* Receive next byte */
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if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
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*data->current.buf = LL_I2C_ReceiveData8(i2c);
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}
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data->current.buf++;
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data->current.len--;
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}
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/* NACK received */
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if (LL_I2C_IsActiveFlag_NACK(i2c)) {
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LL_I2C_ClearFlag_NACK(i2c);
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data->current.is_nack = 1;
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goto end;
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}
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/* STOP received */
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if (LL_I2C_IsActiveFlag_STOP(i2c)) {
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LL_I2C_ClearFlag_STOP(i2c);
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LL_I2C_DisableReloadMode(i2c);
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goto end;
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}
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/* Transfer Complete or Transfer Complete Reload */
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if (LL_I2C_IsActiveFlag_TC(i2c) ||
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LL_I2C_IsActiveFlag_TCR(i2c)) {
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/* Issue stop condition if necessary */
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if (data->current.msg->flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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} else {
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stm32_i2c_disable_transfer_interrupts(dev);
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k_sem_give(&data->device_sync_sem);
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}
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}
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return;
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end:
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stm32_i2c_master_mode_end(dev);
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}
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static int stm32_i2c_error(struct device *dev)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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#if defined(CONFIG_I2C_SLAVE)
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if (data->slave_attached && !data->master_active) {
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/* No need for a slave error function right now. */
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return 0;
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}
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#endif
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if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
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LL_I2C_ClearFlag_ARLO(i2c);
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data->current.is_arlo = 1;
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goto end;
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}
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if (LL_I2C_IsActiveFlag_BERR(i2c)) {
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LL_I2C_ClearFlag_BERR(i2c);
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data->current.is_err = 1;
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goto end;
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}
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return 0;
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end:
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stm32_i2c_master_mode_end(dev);
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return -EIO;
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}
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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void stm32_i2c_combined_isr(void *arg)
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{
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struct device *dev = (struct device *) arg;
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if (stm32_i2c_error(dev)) {
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return;
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}
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stm32_i2c_event(dev);
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}
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#else
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void stm32_i2c_event_isr(void *arg)
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{
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struct device *dev = (struct device *) arg;
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stm32_i2c_event(dev);
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}
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void stm32_i2c_error_isr(void *arg)
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{
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struct device *dev = (struct device *) arg;
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stm32_i2c_error(dev);
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}
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#endif
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int stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, uint16_t slave)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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data->current.len = msg->len;
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data->current.buf = msg->buf;
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data->current.is_write = 1;
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data->current.is_nack = 0;
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data->current.is_err = 0;
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data->current.msg = msg;
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msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
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stm32_i2c_enable_transfer_interrupts(dev);
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LL_I2C_EnableIT_TX(i2c);
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k_sem_take(&data->device_sync_sem, K_FOREVER);
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if (data->current.is_nack || data->current.is_err ||
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data->current.is_arlo) {
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goto error;
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}
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return 0;
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error:
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if (data->current.is_arlo) {
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SYS_LOG_DBG("%s: ARLO %d", __func__,
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data->current.is_arlo);
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data->current.is_arlo = 0;
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}
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if (data->current.is_nack) {
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SYS_LOG_DBG("%s: NACK", __func__);
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data->current.is_nack = 0;
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}
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if (data->current.is_err) {
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SYS_LOG_DBG("%s: ERR %d", __func__,
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data->current.is_err);
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data->current.is_err = 0;
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}
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return -EIO;
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}
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int stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, uint16_t slave)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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data->current.len = msg->len;
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data->current.buf = msg->buf;
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data->current.is_write = 0;
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data->current.is_arlo = 0;
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data->current.is_err = 0;
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data->current.is_nack = 0;
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data->current.msg = msg;
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msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
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stm32_i2c_enable_transfer_interrupts(dev);
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LL_I2C_EnableIT_RX(i2c);
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k_sem_take(&data->device_sync_sem, K_FOREVER);
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if (data->current.is_nack || data->current.is_err ||
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data->current.is_arlo) {
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goto error;
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}
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return 0;
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error:
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if (data->current.is_arlo) {
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SYS_LOG_DBG("%s: ARLO %d", __func__,
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data->current.is_arlo);
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data->current.is_arlo = 0;
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}
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if (data->current.is_nack) {
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SYS_LOG_DBG("%s: NACK", __func__);
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data->current.is_nack = 0;
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}
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if (data->current.is_err) {
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SYS_LOG_DBG("%s: ERR %d", __func__,
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data->current.is_err);
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data->current.is_err = 0;
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}
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return -EIO;
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}
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#else /* !CONFIG_I2C_STM32_INTERRUPT */
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static inline void msg_done(struct device *dev, unsigned int current_msg_flags)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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/* Wait for transfer to complete */
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while (!LL_I2C_IsActiveFlag_TC(i2c) && !LL_I2C_IsActiveFlag_TCR(i2c)) {
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;
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}
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/* Issue stop condition if necessary */
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if (current_msg_flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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while (!LL_I2C_IsActiveFlag_STOP(i2c)) {
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;
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}
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LL_I2C_ClearFlag_STOP(i2c);
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LL_I2C_DisableReloadMode(i2c);
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}
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}
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int stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, uint16_t slave)
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{
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|
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
|
|
I2C_TypeDef *i2c = cfg->i2c;
|
|
unsigned int len = 0;
|
|
u8_t *buf = msg->buf;
|
|
|
|
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
|
|
|
|
len = msg->len;
|
|
while (len) {
|
|
while (1) {
|
|
if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
|
|
break;
|
|
}
|
|
|
|
if (LL_I2C_IsActiveFlag_NACK(i2c)) {
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
LL_I2C_TransmitData8(i2c, *buf);
|
|
buf++;
|
|
len--;
|
|
}
|
|
|
|
msg_done(dev, msg->flags);
|
|
|
|
return 0;
|
|
error:
|
|
LL_I2C_ClearFlag_NACK(i2c);
|
|
SYS_LOG_DBG("%s: NACK", __func__);
|
|
|
|
return -EIO;
|
|
}
|
|
|
|
int stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
|
|
u8_t *next_msg_flags, uint16_t slave)
|
|
{
|
|
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
|
|
I2C_TypeDef *i2c = cfg->i2c;
|
|
unsigned int len = 0;
|
|
u8_t *buf = msg->buf;
|
|
|
|
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
|
|
|
|
len = msg->len;
|
|
while (len) {
|
|
while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
|
|
;
|
|
}
|
|
|
|
*buf = LL_I2C_ReceiveData8(i2c);
|
|
buf++;
|
|
len--;
|
|
}
|
|
|
|
msg_done(dev, msg->flags);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int stm32_i2c_configure_timing(struct device *dev, u32_t clock)
|
|
{
|
|
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
|
|
struct i2c_stm32_data *data = DEV_DATA(dev);
|
|
I2C_TypeDef *i2c = cfg->i2c;
|
|
u32_t i2c_hold_time_min, i2c_setup_time_min;
|
|
u32_t i2c_h_min_time, i2c_l_min_time;
|
|
u32_t presc = 1;
|
|
u32_t timing = 0;
|
|
|
|
switch (I2C_SPEED_GET(data->dev_config)) {
|
|
case I2C_SPEED_STANDARD:
|
|
i2c_h_min_time = 4000;
|
|
i2c_l_min_time = 4700;
|
|
i2c_hold_time_min = 500;
|
|
i2c_setup_time_min = 1250;
|
|
break;
|
|
case I2C_SPEED_FAST:
|
|
i2c_h_min_time = 600;
|
|
i2c_l_min_time = 1300;
|
|
i2c_hold_time_min = 375;
|
|
i2c_setup_time_min = 500;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Calculate period until prescaler matches */
|
|
do {
|
|
u32_t t_presc = clock / presc;
|
|
u32_t ns_presc = NSEC_PER_SEC / t_presc;
|
|
u32_t sclh = i2c_h_min_time / ns_presc;
|
|
u32_t scll = i2c_l_min_time / ns_presc;
|
|
u32_t sdadel = i2c_hold_time_min / ns_presc;
|
|
u32_t scldel = i2c_setup_time_min / ns_presc;
|
|
|
|
if ((sclh - 1) > 255 || (scll - 1) > 255) {
|
|
++presc;
|
|
continue;
|
|
}
|
|
|
|
if (sdadel > 15 || (scldel - 1) > 15) {
|
|
++presc;
|
|
continue;
|
|
}
|
|
|
|
timing = __LL_I2C_CONVERT_TIMINGS(presc - 1,
|
|
scldel - 1, sdadel, sclh - 1, scll - 1);
|
|
break;
|
|
} while (presc < 16);
|
|
|
|
if (presc >= 16) {
|
|
SYS_LOG_DBG("I2C:failed to find prescaler value");
|
|
return -EINVAL;
|
|
}
|
|
|
|
LL_I2C_SetTiming(i2c, timing);
|
|
|
|
return 0;
|
|
}
|