Daniel Leung 7bb5015ced tests: benchmarks: use high-res counter for MEC1501 SoC ... The timer counter for ticks on MEC1501 SoC is based on the RTOS timer which runs at 32kHz. This is too slow for timing benchmarks as most cases can be finished within one or two ticks. Since the SoC has higher frequency timers running at 48MHz, add the necessary bits to use these for timing benchmarks. Fix #23414 Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2020-03-31 19:52:21 -04:00
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arc	kernel: interrupt/idle stacks/threads as array	2020-03-16 23:17:36 +02:00
arm	arm: AArch64: Add support for nested exception handlers	2020-03-31 19:24:48 +02:00
common	tests: benchmarks: use high-res counter for MEC1501 SoC	2020-03-31 19:52:21 -04:00
nios2	kernel: interrupt/idle stacks/threads as array	2020-03-16 23:17:36 +02:00
posix	tracing: move headers under include/tracing	2020-02-07 15:58:05 -05:00
riscv	kernel: interrupt/idle stacks/threads as array	2020-03-16 23:17:36 +02:00
x86	arch: x86: Convert to new DT_INST macros	2020-03-26 03:29:23 -05:00
xtensa	xtensa: add calling entry point for multi-processing	2020-03-25 19:07:28 -04:00
CMakeLists.txt	arch: Simplify private header include path configuration.	2019-11-06 16:07:32 -08:00
Kconfig	kernel: delete separate logic for priv stacks	2020-03-17 20:11:27 +02:00