mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-22 11:25:21 +00:00
The goal of this patch is to replace the 'void *' parameter by 'struct device *' if they use such variable or just 'const void *' on all relevant ISRs This will avoid not-so-nice const qualifier tweaks when device instances will be constant. Note that only the ISR passed to IRQ_CONNECT are of interest here. In order to do so, the script fix_isr.py below is necessary: from pathlib import Path import subprocess import pickle import mmap import sys import re import os cocci_template = """ @r_fix_isr_0 @ type ret_type; identifier P; identifier D; @@ -ret_type <!fn!>(void *P) +ret_type <!fn!>(const struct device *P) { ... ( const struct device *D = (const struct device *)P; | const struct device *D = P; ) ... } @r_fix_isr_1 @ type ret_type; identifier P; identifier D; @@ -ret_type <!fn!>(void *P) +ret_type <!fn!>(const struct device *P) { ... const struct device *D; ... ( D = (const struct device *)P; | D = P; ) ... } @r_fix_isr_2 @ type ret_type; identifier A; @@ -ret_type <!fn!>(void *A) +ret_type <!fn!>(const void *A) { ... } @r_fix_isr_3 @ const struct device *D; @@ -<!fn!>((void *)D); +<!fn!>(D); @r_fix_isr_4 @ type ret_type; identifier D; identifier P; @@ -ret_type <!fn!>(const struct device *P) +ret_type <!fn!>(const struct device *D) { ... ( -const struct device *D = (const struct device *)P; | -const struct device *D = P; ) ... } @r_fix_isr_5 @ type ret_type; identifier D; identifier P; @@ -ret_type <!fn!>(const struct device *P) +ret_type <!fn!>(const struct device *D) { ... -const struct device *D; ... ( -D = (const struct device *)P; | -D = P; ) ... } """ def find_isr(fn): db = [] data = None start = 0 try: with open(fn, 'r+') as f: data = str(mmap.mmap(f.fileno(), 0).read()) except Exception as e: return db while True: isr = "" irq = data.find('IRQ_CONNECT', start) while irq > -1: p = 1 arg = 1 p_o = data.find('(', irq) if p_o < 0: irq = -1 break; pos = p_o + 1 while p > 0: if data[pos] == ')': p -= 1 elif data[pos] == '(': p += 1 elif data[pos] == ',' and p == 1: arg += 1 if arg == 3: isr += data[pos] pos += 1 isr = isr.strip(',\\n\\t ') if isr not in db and len(isr) > 0: db.append(isr) start = pos break if irq < 0: break return db def patch_isr(fn, isr_list): if len(isr_list) <= 0: return for isr in isr_list: tmplt = cocci_template.replace('<!fn!>', isr) with open('/tmp/isr_fix.cocci', 'w') as f: f.write(tmplt) cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn] subprocess.run(cmd) def process_files(path): if path.is_file() and path.suffix in ['.h', '.c']: p = str(path.parent) + '/' + path.name isr_list = find_isr(p) patch_isr(p, isr_list) elif path.is_dir(): for p in path.iterdir(): process_files(p) if len(sys.argv) < 2: print("You need to provide a dir/file path") sys.exit(1) process_files(Path(sys.argv[1])) And is run: ./fix_isr.py <zephyr root directory> Finally, some files needed manual fixes such. Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
316 lines
8.9 KiB
C
316 lines
8.9 KiB
C
/*
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* Copyright (c) 2019 ST Microelectronics Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_ipcc_mailbox
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#include <drivers/clock_control.h>
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#include <device.h>
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#include <errno.h>
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#include <drivers/ipm.h>
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#include <soc.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ipm_stm32_ipcc, CONFIG_IPM_LOG_LEVEL);
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct stm32_ipcc_mailbox_config * const)(dev)->config)
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#define DEV_DATA(dev) \
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((struct stm32_ipcc_mbx_data * const)(dev)->data)
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#define MBX_STRUCT(dev) \
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((IPCC_TypeDef *)(DEV_CFG(dev))->uconf.base)
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#define IPCC_ALL_MR_TXF_CH_MASK 0xFFFF0000
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#define IPCC_ALL_MR_RXO_CH_MASK 0x0000FFFF
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#define IPCC_ALL_SR_CH_MASK 0x0000FFFF
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#if (CONFIG_IPM_STM32_IPCC_PROCID == 1)
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#define IPCC_EnableIT_TXF(hipcc) LL_C1_IPCC_EnableIT_TXF(hipcc)
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#define IPCC_DisableIT_TXF(hipcc) LL_C1_IPCC_DisableIT_TXF(hipcc)
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#define IPCC_EnableIT_RXO(hipcc) LL_C1_IPCC_EnableIT_RXO(hipcc)
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#define IPCC_DisableIT_RXO(hipcc) LL_C1_IPCC_DisableIT_RXO(hipcc)
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#define IPCC_EnableReceiveChannel(hipcc, ch) \
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LL_C1_IPCC_EnableReceiveChannel(hipcc, 1 << ch)
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#define IPCC_EnableTransmitChannel(hipcc, ch) \
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LL_C1_IPCC_EnableTransmitChannel(hipcc, 1 << ch)
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#define IPCC_DisableReceiveChannel(hipcc, ch) \
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LL_C2_IPCC_DisableReceiveChannel(hipcc, 1 << ch)
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#define IPCC_DisableTransmitChannel(hipcc, ch) \
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LL_C1_IPCC_DisableTransmitChannel(hipcc, 1 << ch)
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#define IPCC_ClearFlag_CHx(hipcc, ch) LL_C1_IPCC_ClearFlag_CHx(hipcc, 1 << ch)
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#define IPCC_SetFlag_CHx(hipcc, ch) LL_C1_IPCC_SetFlag_CHx(hipcc, 1 << ch)
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#define IPCC_IsActiveFlag_CHx(hipcc, ch) \
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LL_C1_IPCC_IsActiveFlag_CHx(hipcc, 1 << ch)
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#define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C1##reg)
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#define IPCC_ReadReg_SR(hipcc) READ_REG(hipcc->C1TOC2SR)
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#define IPCC_ReadOtherInstReg_SR(hipcc) READ_REG(hipcc->C2TOC1SR)
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#else
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#define IPCC_EnableIT_TXF(hipcc) LL_C2_IPCC_EnableIT_TXF(hipcc)
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#define IPCC_DisableIT_TXF(hipcc) LL_C2_IPCC_DisableIT_TXF(hipcc)
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#define IPCC_EnableIT_RXO(hipcc) LL_C2_IPCC_EnableIT_RXO(hipcc)
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#define IPCC_DisableIT_RXO(hipcc) LL_C2_IPCC_DisableIT_RXO(hipcc)
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#define IPCC_EnableReceiveChannel(hipcc, ch) \
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LL_C2_IPCC_EnableReceiveChannel(hipcc, 1 << ch)
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#define IPCC_EnableTransmitChannel(hipcc, ch) \
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LL_C2_IPCC_EnableTransmitChannel(hipcc, 1 << ch)
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#define IPCC_DisableReceiveChannel(hipcc, ch) \
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LL_C2_IPCC_DisableReceiveChannel(hipcc, 1 << ch)
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#define IPCC_DisableTransmitChannel(hipcc, ch) \
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LL_C2_IPCC_DisableTransmitChannel(hipcc, 1 << ch)
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#define IPCC_ClearFlag_CHx(hipcc, ch) LL_C2_IPCC_ClearFlag_CHx(hipcc, 1 << ch)
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#define IPCC_SetFlag_CHx(hipcc, ch) LL_C2_IPCC_SetFlag_CHx(hipcc, 1 << ch)
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#define IPCC_IsActiveFlag_CHx(hipcc, ch) \
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LL_C2_IPCC_IsActiveFlag_CHx(hipcc, 1 << ch)
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#define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C2##reg)
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#define IPCC_ReadReg_SR(hipcc) READ_REG(hipcc->C2TOC1SR)
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#define IPCC_ReadOtherInstReg_SR(hipcc) READ_REG(hipcc->C1TOC2SR)
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#endif
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struct stm32_ipcc_mailbox_config {
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void (*irq_config_func)(const struct device *dev);
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IPCC_TypeDef *ipcc;
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struct stm32_pclken pclken;
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};
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struct stm32_ipcc_mbx_data {
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uint32_t num_ch;
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ipm_callback_t callback;
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void *user_data;
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};
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static struct stm32_ipcc_mbx_data stm32_IPCC_data;
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static void stm32_ipcc_mailbox_rx_isr(const struct device *dev)
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{
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struct stm32_ipcc_mbx_data *data = DEV_DATA(dev);
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const struct stm32_ipcc_mailbox_config *cfg = DEV_CFG(dev);
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unsigned int value = 0;
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uint32_t mask, i;
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mask = (~IPCC_ReadReg(cfg->ipcc, MR)) & IPCC_ALL_MR_RXO_CH_MASK;
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mask &= IPCC_ReadOtherInstReg_SR(cfg->ipcc) & IPCC_ALL_SR_CH_MASK;
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for (i = 0; i < data->num_ch; i++) {
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if (!((1 << i) & mask)) {
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continue;
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}
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LOG_DBG("%s channel = %x\r\n", __func__, i);
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/* mask the channel Free interrupt */
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IPCC_DisableReceiveChannel(cfg->ipcc, i);
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if (data->callback) {
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/* Only one MAILBOX, id is unused and set to 0 */
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data->callback(dev, data->user_data, i, &value);
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}
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/* clear status to acknoledge message reception */
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IPCC_ClearFlag_CHx(cfg->ipcc, i);
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IPCC_EnableReceiveChannel(cfg->ipcc, i);
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}
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}
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static void stm32_ipcc_mailbox_tx_isr(const struct device *dev)
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{
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struct stm32_ipcc_mbx_data *data = DEV_DATA(dev);
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const struct stm32_ipcc_mailbox_config *cfg = DEV_CFG(dev);
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uint32_t mask, i;
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mask = (~IPCC_ReadReg(cfg->ipcc, MR)) & IPCC_ALL_MR_TXF_CH_MASK;
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mask = mask >> IPCC_C1MR_CH1FM_Pos;
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mask &= IPCC_ReadReg_SR(cfg->ipcc) & IPCC_ALL_SR_CH_MASK;
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for (i = 0; i < data->num_ch; i++) {
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if (!((1 << i) & mask)) {
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continue;
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}
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LOG_DBG("%s channel = %x\r\n", __func__, i);
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/* mask the channel Free interrupt */
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IPCC_DisableTransmitChannel(cfg->ipcc, i);
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}
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}
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static int stm32_ipcc_mailbox_ipm_send(const struct device *dev, int wait,
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uint32_t id,
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const void *buff, int size)
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{
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struct stm32_ipcc_mbx_data *data = dev->data;
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const struct stm32_ipcc_mailbox_config *cfg = DEV_CFG(dev);
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ARG_UNUSED(wait);
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ARG_UNUSED(buff);
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/* No data transmition, only doorbell */
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if (size) {
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return -EMSGSIZE;
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}
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if (id >= data->num_ch) {
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LOG_ERR("invalid id (%d)\r\n", id);
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return -EINVAL;
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}
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LOG_DBG("Send msg on channel %d\r\n", id);
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/* Check that the channel is free (otherwise wait) */
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if (IPCC_IsActiveFlag_CHx(cfg->ipcc, id)) {
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LOG_DBG("Waiting for channel to be freed\r\n");
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while (IPCC_IsActiveFlag_CHx(cfg->ipcc, id)) {
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;
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}
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}
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IPCC_EnableTransmitChannel(cfg->ipcc, id);
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IPCC_SetFlag_CHx(cfg->ipcc, id);
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return 0;
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}
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static int stm32_ipcc_mailbox_ipm_max_data_size_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* no data transfer capability */
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return 0;
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}
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static uint32_t stm32_ipcc_mailbox_ipm_max_id_val_get(const struct device *d)
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{
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struct stm32_ipcc_mbx_data *data = DEV_DATA(d);
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return data->num_ch - 1;
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}
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static void stm32_ipcc_mailbox_ipm_register_callback(const struct device *d,
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ipm_callback_t cb,
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void *user_data)
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{
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struct stm32_ipcc_mbx_data *data = DEV_DATA(d);
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data->callback = cb;
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data->user_data = user_data;
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}
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static int stm32_ipcc_mailbox_ipm_set_enabled(const struct device *dev,
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int enable)
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{
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struct stm32_ipcc_mbx_data *data = DEV_DATA(dev);
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const struct stm32_ipcc_mailbox_config *cfg = DEV_CFG(dev);
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uint32_t i;
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/* For now: nothing to be done */
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LOG_DBG("%s %s mailbox\r\n", __func__, enable ? "enable" : "disable");
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if (enable) {
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/* Enable RX and TX interrupts */
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IPCC_EnableIT_TXF(cfg->ipcc);
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IPCC_EnableIT_RXO(cfg->ipcc);
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for (i = 0; i < data->num_ch; i++) {
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IPCC_EnableReceiveChannel(cfg->ipcc, i);
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}
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} else {
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/* Disable RX and TX interrupts */
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IPCC_DisableIT_TXF(cfg->ipcc);
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IPCC_DisableIT_RXO(cfg->ipcc);
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for (i = 0; i < data->num_ch; i++) {
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IPCC_DisableReceiveChannel(cfg->ipcc, i);
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}
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}
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return 0;
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}
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static int stm32_ipcc_mailbox_init(const struct device *dev)
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{
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struct stm32_ipcc_mbx_data *data = DEV_DATA(dev);
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const struct stm32_ipcc_mailbox_config *cfg = DEV_CFG(dev);
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const struct device *clk;
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uint32_t i;
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clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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/* enable clock */
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if (clock_control_on(clk,
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(clock_control_subsys_t *)&cfg->pclken) != 0) {
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return -EIO;
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}
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/* Disable RX and TX interrupts */
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IPCC_DisableIT_TXF(cfg->ipcc);
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IPCC_DisableIT_RXO(cfg->ipcc);
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data->num_ch = LL_IPCC_GetChannelConfig(cfg->ipcc);
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for (i = 0; i < data->num_ch; i++) {
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/* Clear RX status */
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IPCC_ClearFlag_CHx(cfg->ipcc, i);
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/* mask RX and TX interrupts */
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IPCC_DisableReceiveChannel(cfg->ipcc, i);
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IPCC_DisableTransmitChannel(cfg->ipcc, i);
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}
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cfg->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api stm32_ipcc_mailbox_driver_api = {
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.send = stm32_ipcc_mailbox_ipm_send,
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.register_callback = stm32_ipcc_mailbox_ipm_register_callback,
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.max_data_size_get = stm32_ipcc_mailbox_ipm_max_data_size_get,
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.max_id_val_get = stm32_ipcc_mailbox_ipm_max_id_val_get,
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.set_enabled = stm32_ipcc_mailbox_ipm_set_enabled,
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};
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static void stm32_ipcc_mailbox_config_func(const struct device *dev);
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/* Config MAILBOX 0 */
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static const struct stm32_ipcc_mailbox_config stm32_ipcc_mailbox_0_config = {
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.irq_config_func = stm32_ipcc_mailbox_config_func,
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.ipcc = (IPCC_TypeDef *)DT_INST_REG_ADDR(0),
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.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
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.enr = DT_INST_CLOCKS_CELL(0, bits)
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},
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};
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DEVICE_AND_API_INIT(mailbox_0, DT_INST_LABEL(0),
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&stm32_ipcc_mailbox_init,
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&stm32_IPCC_data, &stm32_ipcc_mailbox_0_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&stm32_ipcc_mailbox_driver_api);
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static void stm32_ipcc_mailbox_config_func(const struct device *dev)
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{
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, rxo, irq),
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DT_INST_IRQ_BY_NAME(0, rxo, priority),
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stm32_ipcc_mailbox_rx_isr, DEVICE_GET(mailbox_0), 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, txf, irq),
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DT_INST_IRQ_BY_NAME(0, txf, priority),
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stm32_ipcc_mailbox_tx_isr, DEVICE_GET(mailbox_0), 0);
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irq_enable(DT_INST_IRQ_BY_NAME(0, rxo, irq));
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irq_enable(DT_INST_IRQ_BY_NAME(0, txf, irq));
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}
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