mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 03:42:47 +00:00
e8d0eb1db1
This commits adds GPIO driver for LiteX SoC builder. Due to the fact that GPIO in LiteX is unidirectional and can be configured with different pins amount per port, additional entries were added to the dts file. Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
316 lines
7.3 KiB
C
316 lines
7.3 KiB
C
/*
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* Copyright (c) 2019 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <zephyr/types.h>
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#include <sys/util.h>
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#include <string.h>
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#include <logging/log.h>
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#define SUPPORTED_FLAGS (GPIO_INPUT | GPIO_OUTPUT | \
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GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | \
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GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH)
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#define GPIO_LOW 0
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#define GPIO_HIGH 1
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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LOG_MODULE_REGISTER(gpio_litex);
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static const char *LITEX_LOG_REG_SIZE_NGPIOS_MISMATCH =
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"Cannot handle all of the gpios with the register of given size\n";
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static const char *LITEX_LOG_WRONG_DIR =
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"Direction chosen in device tree do not match with the operation\n";
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static const char *LITEX_LOG_CANNOT_CHANGE_DIR =
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"Cannot change port direction selected in device tree\n";
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struct gpio_litex_cfg {
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volatile u32_t *reg_addr;
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int reg_size;
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int nr_gpios;
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bool port_is_output;
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};
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struct gpio_litex_data {
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struct gpio_driver_data common;
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};
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/* Helper macros for GPIO */
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#define DEV_GPIO_CFG(dev) \
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((const struct gpio_litex_cfg *)(dev)->config->config_info)
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/* Helper functions for bit / port access */
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static inline void set_bit(const struct gpio_litex_cfg *config,
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u32_t bit, bool val)
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{
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int regv, new_regv;
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regv = litex_read(config->reg_addr, config->reg_size);
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new_regv = (regv & ~BIT(bit)) | (val << bit);
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litex_write(config->reg_addr, config->reg_size, new_regv);
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}
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static inline u32_t get_bit(const struct gpio_litex_cfg *config, u32_t bit)
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{
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int regv = litex_read(config->reg_addr, config->reg_size);
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return !!(regv & BIT(bit));
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}
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static inline void set_port(const struct gpio_litex_cfg *config, u32_t value)
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{
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litex_write(config->reg_addr, config->reg_size, value);
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}
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static inline u32_t get_port(const struct gpio_litex_cfg *config)
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{
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int regv = litex_read(config->reg_addr, config->reg_size);
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return (regv & BIT_MASK(config->nr_gpios));
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}
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/* Driver functions */
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static int gpio_litex_init(struct device *dev)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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/* each 4-byte register is able to handle 8 GPIO pins */
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if (gpio_config->nr_gpios > (gpio_config->reg_size / 4) * 8) {
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LOG_ERR("%s", LITEX_LOG_REG_SIZE_NGPIOS_MISMATCH);
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return -EINVAL;
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}
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return 0;
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}
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static int gpio_litex_configure(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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if (flags & ~SUPPORTED_FLAGS) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
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/* Pin cannot be configured as input and output */
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return -ENOTSUP;
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} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
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/* Pin has to be configuread as input or output */
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT) {
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if (!gpio_config->port_is_output) {
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LOG_ERR("%s", LITEX_LOG_CANNOT_CHANGE_DIR);
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return -EINVAL;
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}
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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set_bit(gpio_config, pin, GPIO_HIGH);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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set_bit(gpio_config, pin, GPIO_LOW);
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}
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} else {
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if (gpio_config->port_is_output) {
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LOG_ERR("%s", LITEX_LOG_CANNOT_CHANGE_DIR);
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return -EINVAL;
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}
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}
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return 0;
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}
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static int gpio_litex_write(struct device *dev, int access_op,
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u32_t pin, u32_t value)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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if (!gpio_config->port_is_output) {
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LOG_ERR("%s", LITEX_LOG_WRONG_DIR);
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return -EINVAL;
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}
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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set_bit(gpio_config, pin, value);
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return 0;
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}
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static int gpio_litex_read(struct device *dev, int access_op,
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u32_t pin, u32_t *value)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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*value = get_bit(gpio_config, pin);
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return 0;
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}
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static int gpio_litex_port_get_raw(struct device *dev, gpio_port_value_t *value)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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*value = get_port(gpio_config);
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return 0;
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}
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static int gpio_litex_port_set_masked_raw(struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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u32_t port_val;
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port_val = get_port(gpio_config);
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port_val = (port_val & ~mask) | (value & mask);
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set_port(gpio_config, port_val);
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return 0;
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}
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static int gpio_litex_port_set_bits_raw(struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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u32_t port_val;
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port_val = get_port(gpio_config);
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port_val |= pins;
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set_port(gpio_config, port_val);
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return 0;
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}
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static int gpio_litex_port_clear_bits_raw(struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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u32_t port_val;
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port_val = get_port(gpio_config);
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port_val &= ~pins;
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set_port(gpio_config, port_val);
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return 0;
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}
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static int gpio_litex_port_toggle_bits(struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
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u32_t port_val;
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port_val = get_port(gpio_config);
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port_val ^= pins;
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set_port(gpio_config, port_val);
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return 0;
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}
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static int gpio_litex_pin_interrupt_configure(struct device *dev,
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unsigned int pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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int ret = 0;
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if (mode != GPIO_INT_MODE_DISABLED) {
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ret = -ENOTSUP;
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}
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return ret;
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}
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static const struct gpio_driver_api gpio_litex_driver_api = {
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.config = gpio_litex_configure,
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.write = gpio_litex_write,
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.read = gpio_litex_read,
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.port_get_raw = gpio_litex_port_get_raw,
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.port_set_masked_raw = gpio_litex_port_set_masked_raw,
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.port_set_bits_raw = gpio_litex_port_set_bits_raw,
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.port_clear_bits_raw = gpio_litex_port_clear_bits_raw,
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.port_toggle_bits = gpio_litex_port_toggle_bits,
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.pin_interrupt_configure = gpio_litex_pin_interrupt_configure,
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};
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/* Device Instantiation */
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#define GPIO_LITEX_INIT(n) \
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BUILD_ASSERT_MSG(DT_INST_##n##_LITEX_GPIO_SIZE != 0 \
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&& DT_INST_##n##_LITEX_GPIO_SIZE % 4 == 0, \
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"Register size must be a multiple of 4"); \
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\
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static const struct gpio_litex_cfg gpio_litex_cfg_##n = { \
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.reg_addr = \
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(volatile u32_t *) DT_INST_##n##_LITEX_GPIO_BASE_ADDRESS, \
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.reg_size = DT_INST_##n##_LITEX_GPIO_SIZE, \
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.nr_gpios = DT_INST_##n##_LITEX_GPIO_NGPIOS, \
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.port_is_output = DT_INST_##n##_LITEX_GPIO_PORT_IS_OUTPUT, \
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}; \
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static struct gpio_litex_data gpio_litex_data_##n; \
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\
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DEVICE_AND_API_INIT(litex_gpio_##n, \
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DT_INST_##n##_LITEX_GPIO_LABEL, \
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gpio_litex_init, \
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&gpio_litex_data_##n, \
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&gpio_litex_cfg_##n, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_litex_driver_api \
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)
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#ifdef DT_INST_0_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(0);
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#endif
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#ifdef DT_INST_1_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(1);
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#endif
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#ifdef DT_INST_2_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(2);
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#endif
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#ifdef DT_INST_3_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(3);
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#endif
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#ifdef DT_INST_4_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(4);
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#endif
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#ifdef DT_INST_5_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(5);
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#endif
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#ifdef DT_INST_6_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(6);
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#endif
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#ifdef DT_INST_7_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(7);
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#endif
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#ifdef DT_INST_8_LITEX_GPIO_LABEL
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GPIO_LITEX_INIT(8);
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#endif
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