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https://github.com/zephyrproject-rtos/zephyr
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77db273f6f
STM32 clock control subsystem allows to configure a different frequency value for core clock (SYSCLK) and AHB clock (HCLK). Though, it is HCLK which is used to feed Cortex Systick timer which is used in zephyr as reference system clock. If HCLK frequency is configured to a different value from SYSCLK frequency, whole system is exposed to desynchro between zephyr clock subsytem and STM32 HW configuration. To prevent this, and until zephyr clock subsystem is changed to be aware of this potential configuration, enforce AHB prescaler value to 1 (which is current default value in use for all STM32 based boards). On STM32H7, enforce D1CPRE which fills the same role as ABH precaler. On STM32MP1, the equivalent setting is done on A7 core, so it is not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC is set with the 'mlhclk_ck' clock frequency value. Update matching boards documentation. Fixes #17188 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org> |
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| .. | ||
| beetle_clock_control.c | ||
| clock_control_mcux_ccm.c | ||
| clock_control_mcux_pcc.c | ||
| clock_control_mcux_scg.c | ||
| clock_control_mcux_sim.c | ||
| clock_control_rv32m1_pcc.c | ||
| clock_stm32_ll_common.c | ||
| clock_stm32_ll_common.h | ||
| clock_stm32_ll_h7.c | ||
| clock_stm32_ll_mp1.c | ||
| clock_stm32f1.c | ||
| clock_stm32f2_f4_f7.c | ||
| clock_stm32f0_f3.c | ||
| clock_stm32g0.c | ||
| clock_stm32l4_wb.c | ||
| clock_stm32l0_l1.c | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.beetle | ||
| Kconfig.mcux_ccm | ||
| Kconfig.mcux_pcc | ||
| Kconfig.mcux_scg | ||
| Kconfig.mcux_sim | ||
| Kconfig.nrf | ||
| Kconfig.rv32m1 | ||
| Kconfig.stm32 | ||
| Kconfig.stm32f1 | ||
| Kconfig.stm32f2_f4_f7 | ||
| Kconfig.stm32f0_f3 | ||
| Kconfig.stm32g0 | ||
| Kconfig.stm32h7 | ||
| Kconfig.stm32l4_wb | ||
| Kconfig.stm32l0_l1 | ||
| nrf_power_clock.c | ||