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https://github.com/zephyrproject-rtos/zephyr
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c6d527bc4b
This adds the I2C driver for the Sensor Subsystem on Quark SE. This provides minimal support for the I2C controller, and does only synchronous transfer at the moment. Change-Id: I400b8ff3390d4b641bed5b8c617830c4217de3ff Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Header for I2C driver for Quark SE Sensor Subsystem
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*/
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#ifndef __DRIVERS_I2C_QUARK_SE_SS_H__
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#define __DRIVERS_I2C_QUARK_SE_SS_H__
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#include <i2c.h>
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#include <stdbool.h>
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/* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */
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#define I2C_QSE_SS_STATE_READY (0)
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#define I2C_QSE_SS_CMD_SEND (1 << 0)
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#define I2C_QSE_SS_CMD_RECV (1 << 1)
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#define I2C_QSE_SS_CMD_ERROR (1 << 2)
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#define I2C_QSE_SS_BUSY (1 << 3)
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/*
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* DesignWare speed values don't directly translate from the Zephyr speed
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* selections in include/i2c.h so here we do a little translation
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*/
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#define I2C_QSE_SS_SPEED_STANDARD 0x1
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#define I2C_QSE_SS_SPEED_FAST 0x2
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#define I2C_QSE_SS_SPEED_FAST_PLUS 0x2
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/* IC_CON Low count and high count default values */
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/* TODO verify all values for Quark SE SS */
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#define I2C_STD_HCNT (CONFIG_I2C_CLOCK_SPEED * 4)
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#define I2C_STD_LCNT (CONFIG_I2C_CLOCK_SPEED * 5)
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#define I2C_FS_HCNT ((CONFIG_I2C_CLOCK_SPEED * 6) / 8)
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#define I2C_FS_LCNT ((CONFIG_I2C_CLOCK_SPEED * 7) / 8)
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typedef void (*i2c_qse_ss_cfg_func_t)(struct device *port);
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struct i2c_qse_ss_rom_config {
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uint32_t base_address;
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i2c_qse_ss_cfg_func_t config_func;
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/* IRQ for ERR (error) conditions */
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uint32_t isr_err_vector;
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uint32_t isr_err_mask;
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/* IRQ for RX_AVAIL */
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uint32_t isr_rx_vector;
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uint32_t isr_rx_mask;
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/* IRQ for TX_REQ */
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uint32_t isr_tx_vector;
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uint32_t isr_tx_mask;
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/* IRQ for STOP_DET */
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uint32_t isr_stop_vector;
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uint32_t isr_stop_mask;
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};
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struct i2c_qse_ss_dev_config {
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union dev_config app_config;
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volatile uint8_t state; /* last direction of transfer */
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uint8_t request_bytes;
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uint8_t rx_len;
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uint8_t *rx_buffer;
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uint8_t tx_len;
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uint8_t *tx_buffer;
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uint16_t hcnt;
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uint16_t lcnt;
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};
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#endif /* __DRIVERS_I2C_QUARK_SE_SS_H__ */
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