Daniel Leung e4aa946c55 timer: xtensa_sys_timer: set compare register at init ... Since CCOMPARE* registers have undefined values after reset, set compare value first before enabling timer interrupt. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2018-11-03 12:40:33 -04:00
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altera_avalon_timer_hal.c
arcv2_timer0.c
CMakeLists.txt
cortex_m_systick.c
hpet.c
Kconfig
legacy_api.h
loapic_timer.c
native_posix_timer.c
nrf_rtc_timer.c
pulpino_timer.c
riscv_machine_timer.c
sys_clock_init.c
xtensa_sys_timer.c	timer: xtensa_sys_timer: set compare register at init	2018-11-03 12:40:33 -04:00