Dong Wang 0afddb2341 x86/cache: fix issues in arch dcache flush function ... Correct the wrong operand of clflush instruction. The old operand points to a location inside stack and doesn't work. The new one works well by taking linux kernel code as reference. End address instead of size should get round up Add Kconfig option to disable the usage of mfence intruction for SoC that has clfulsh but no mfence supported. Signed-off-by: Dong Wang <dong.d.wang@intel.com>		2021-08-30 09:16:39 -04:00
..
arc	ARC: save/restore accumulator registers on all ARCv2 HS CPUs by default	2021-07-06 21:29:22 -04:00
arm	arch: arm: cortex-m: add support for clearing NXP MPU regions at boot	2021-05-26 18:14:03 -05:00
arm64	arch: arm64: Fix the assertion failed when MP_NUM_CPUS >= 3	2021-05-26 04:42:49 -05:00
common
nios2
posix
riscv
sparc	SPARC: add the Flush windows software trap	2021-05-28 06:32:36 -05:00
x86	x86/cache: fix issues in arch dcache flush function	2021-08-30 09:16:39 -04:00
xtensa
CMakeLists.txt
Kconfig	kernel: mmu: z_backing_store* to k_mem_paging_backing_store*	2021-05-28 11:33:22 -04:00