mirror of
https://github.com/zephyrproject-rtos/zephyr
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70d819b405
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
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* Copyright (c) 2018, Diego Sueiro
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SOC_CLOCK_FREQ_H__
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#define __SOC_CLOCK_FREQ_H__
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#include "device_imx.h"
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#include <zephyr/types.h>
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#ifdef CONFIG_PWM_IMX
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/*!
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* @brief Get clock frequency applies to the PWM module
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*
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* @param base PWM base pointer.
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* @return clock frequency (in HZ) applies to the PWM module
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*/
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u32_t get_pwm_clock_freq(PWM_Type *base);
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#endif /* CONFIG_PWM_IMX */
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#if defined(__cplusplus)
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}
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#endif
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/*! @brief Root control names for root clock setting. */
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enum _ccm_root_control_extra {
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ccmRootPwm1 = (u32_t)(&CCM_TARGET_ROOT106),
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ccmRootPwm2 = (u32_t)(&CCM_TARGET_ROOT107),
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ccmRootPwm3 = (u32_t)(&CCM_TARGET_ROOT108),
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ccmRootPwm4 = (u32_t)(&CCM_TARGET_ROOT109),
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};
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/*! @brief Clock source enumeration for PWM peripheral. */
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enum _ccm_rootmux_pwm {
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ccmRootmuxPwmOsc24m = 0U,
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ccmRootmuxPwmEnetPllDiv10 = 1U,
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ccmRootmuxPwmSysPllDiv4 = 2U,
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ccmRootmuxPwmEnetPllDiv25 = 3U,
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ccmRootmuxPwmAudioPll = 4U,
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ccmRootmuxPwmExtClk2 = 5U,
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ccmRootmuxPwmRef1m = 6U,
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ccmRootmuxPwmVideoPll = 7U,
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};
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/*! @brief CCM CCGR gate control. */
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enum _ccm_ccgr_gate_extra {
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ccmCcgrGatePwm1 = (u32_t)(&CCM_CCGR132),
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ccmCcgrGatePwm2 = (u32_t)(&CCM_CCGR133),
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ccmCcgrGatePwm3 = (u32_t)(&CCM_CCGR134),
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ccmCcgrGatePwm4 = (u32_t)(&CCM_CCGR135),
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};
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#endif /* __SOC_CLOCK_FREQ_H__ */
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