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https://github.com/zephyrproject-rtos/zephyr
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0b9c584ec1
Set stm32_dt_pinctrl_configure function as the unique entry point to STM32 DT pinctrl management. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
208 lines
5.5 KiB
C
208 lines
5.5 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file header for STM32 pin multiplexing
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*/
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#ifndef ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32_H_
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#define ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32_H_
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#include <zephyr/types.h>
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#include <stddef.h>
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#include <drivers/clock_control.h>
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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#include <dt-bindings/pinctrl/stm32f1-pinctrl.h>
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#else
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#include <dt-bindings/pinctrl/stm32-pinctrl.h>
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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#include "pinmux/pinmux.h"
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/**
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* @brief structure to convey pinctrl information for stm32 soc
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* value
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*/
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struct soc_gpio_pinctrl {
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uint32_t pinmux;
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uint32_t pincfg;
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};
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/**
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* @brief helper to extract IO port number from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_PORT(__pin) \
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(((__pin) >> 12) & 0xf)
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/**
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* @brief helper to extract IO pin number from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_LINE(__pin) \
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(((__pin) >> 8) & 0xf)
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/**
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* @brief helper to extract IO pin func from STM32_PINMUX() encoded
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* value
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*/
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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#define STM32_DT_PINMUX_FUNC(__pin) \
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(((__pin) >> 6) & 0x3)
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#else
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#define STM32_DT_PINMUX_FUNC(__pin) \
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((__pin) & 0xff)
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/**
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* @brief helper to extract IO pin remap from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_REMAP(__pin) \
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((__pin) & 0x1f)
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#endif
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/* pretend that array will cover pin functions */
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typedef int stm32_pin_func_t;
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/**
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* @brief pinmux config wrapper
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*
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* GPIO function is assumed to be always available, as such it's not listed
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* in @funcs array
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*/
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struct stm32_pinmux_conf {
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uint32_t pin; /* pin ID */
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const stm32_pin_func_t *funcs; /* functions array, indexed with
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* (stm32_pin_alt_func - 1)
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*/
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const size_t nfuncs; /* number of alternate functions, not
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* counting GPIO
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*/
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};
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/**
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* @brief helper to extract IO port number from STM32PIN() encoded
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* value
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*/
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#define STM32_PORT(__pin) \
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((__pin) >> 4)
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/**
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* @brief helper to extract IO pin number from STM32PIN() encoded
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* value
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*/
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#define STM32_PIN(__pin) \
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((__pin) & 0xf)
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/**
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* @brief helper for mapping IO port to its clock subsystem
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*
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* @param port IO port
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*
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* Map given IO @port to corresponding clock subsystem. The returned
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* clock subsystem ID must suitable for passing as parameter to
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* clock_control_on(). Implement this function at the SoC level.
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*
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* @return clock subsystem ID
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*/
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clock_control_subsys_t stm32_get_port_clock(int port);
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/**
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* @brief helper for configuration of IO pin
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*
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* @param pin IO pin, STM32PIN() encoded
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* @param func IO function encoded
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* @param clk clock control device, for enabling/disabling clock gate
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* for the port
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*/
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int z_pinmux_stm32_set(uint32_t pin, uint32_t func,
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const struct device *clk);
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/**
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* @brief helper for obtaining pin configuration for the board
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*
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* @param[out] pins set to the number of pins in the array
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*
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* Obtain pin assignment/configuration for current board. This call
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* needs to be implemented at the board integration level. After
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* restart all pins are already configured as GPIO and can be skipped
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* in the configuration array. Pin numbers in @pin_num field are
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* STM32PIN() encoded.
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*
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*/
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void stm32_setup_pins(const struct pin_config *pinconf,
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size_t pins);
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/**
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* @brief helper for converting dt stm32 pinctrl format to existing pin config
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* format
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*
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* @param *pinctrl pointer to soc_gpio_pinctrl list
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* @param list_size list size
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* @param base device base register value
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*
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* @return 0 on success, -EINVAL otherwise
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*/
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int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
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size_t list_size, uint32_t base);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/**
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* @brief Helper function to check and apply provided pinctrl remap
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* configuration
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*
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* Check operation verifies that pin remapping configuration is the same on all
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* pins. If configuration is valid AFIO clock is enabled and remap is applied
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*
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* @param *pinctrl pointer to soc_gpio_pinctrl list
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* @param list_size list size
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* @param base device base register value
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*
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* @return 0 value on success, -EINVAL otherwise
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*/
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int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
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size_t list_size, uint32_t base);
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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/* common pinmux device name for all STM32 chips */
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#define STM32_PINMUX_NAME "stm32-pinmux"
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#ifdef CONFIG_SOC_SERIES_STM32F0X
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#include "pinmux_stm32f0.h"
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#elif CONFIG_SOC_SERIES_STM32F1X
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#include "pinmux_stm32f1.h"
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#elif CONFIG_SOC_SERIES_STM32F2X
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#include "pinmux_stm32f2.h"
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#elif CONFIG_SOC_SERIES_STM32F3X
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#include "pinmux_stm32f3.h"
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#elif CONFIG_SOC_SERIES_STM32F4X
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#include "pinmux_stm32f4.h"
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#elif CONFIG_SOC_SERIES_STM32F7X
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#include "pinmux_stm32f7.h"
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#elif CONFIG_SOC_SERIES_STM32H7X
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#include "pinmux_stm32h7.h"
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#elif CONFIG_SOC_SERIES_STM32G0X
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#include "pinmux_stm32g0.h"
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#elif CONFIG_SOC_SERIES_STM32G4X
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#include "pinmux_stm32g4x.h"
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#elif CONFIG_SOC_SERIES_STM32L0X
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#include "pinmux_stm32l0.h"
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#elif CONFIG_SOC_SERIES_STM32L1X
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#include "pinmux_stm32l1x.h"
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#elif CONFIG_SOC_SERIES_STM32L4X
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#include "pinmux_stm32l4x.h"
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#elif CONFIG_SOC_SERIES_STM32L5X
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#include "pinmux_stm32l5x.h"
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#elif CONFIG_SOC_SERIES_STM32MP1X
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#include "pinmux_stm32mp1x.h"
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#elif CONFIG_SOC_SERIES_STM32WBX
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#include "pinmux_stm32wbx.h"
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#endif
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#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32_H_ */
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