mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-10 07:21:56 +00:00
70d819b405
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
143 lines
3.2 KiB
C
143 lines
3.2 KiB
C
/*
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* Copyright (c) Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief
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*
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* Based on reference manual:
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* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 8: General-purpose I/Os (GPIOs)
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*/
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#include <errno.h>
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#include <device.h>
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#include "soc.h"
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#include "soc_registers.h"
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#include <gpio.h>
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#include <gpio/gpio_stm32.h>
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int stm32_gpio_flags_to_conf(int flags, int *pincfg)
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{
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int direction = flags & GPIO_DIR_MASK;
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int pud = flags & GPIO_PUD_MASK;
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if (!pincfg) {
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return -EINVAL;
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}
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if (direction == GPIO_DIR_OUT) {
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*pincfg = STM32_MODER_OUTPUT_MODE;
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} else {
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/* pull-{up,down} maybe? */
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*pincfg = STM32_MODER_INPUT_MODE;
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if (pud == GPIO_PUD_PULL_UP) {
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*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
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} else if (pud == GPIO_PUD_PULL_DOWN) {
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*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
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} else {
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/* floating */
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*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
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}
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}
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return 0;
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}
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int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
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{
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volatile struct stm32f4x_gpio *gpio =
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(struct stm32f4x_gpio *)(base_addr);
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unsigned int mode, otype, ospeed, pupd;
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unsigned int pin_shift = pin << 1;
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unsigned int afr_bank = pin / 8;
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unsigned int afr_shift = (pin % 8) << 2;
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u32_t scratch;
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mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
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otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
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ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
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pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
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scratch = gpio->mode & ~(STM32_MODER_MASK << pin_shift);
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gpio->mode = scratch | (mode << pin_shift);
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scratch = gpio->ospeed & ~(STM32_OSPEEDR_MASK << pin_shift);
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gpio->ospeed = scratch | (ospeed << pin_shift);
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scratch = gpio->otype & ~(STM32_OTYPER_MASK << pin);
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gpio->otype = scratch | (otype << pin);
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scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
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gpio->pupdr = scratch | (pupd << pin_shift);
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scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
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gpio->afr[afr_bank] = scratch | (altf << afr_shift);
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return 0;
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}
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int stm32_gpio_set(u32_t *base, int pin, int value)
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{
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struct stm32f4x_gpio *gpio = (struct stm32f4x_gpio *)base;
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if (value) {
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/* atomic set */
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gpio->bsr = (1 << (pin & 0x0f));
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} else {
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/* atomic reset */
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gpio->bsr = (1 << ((pin & 0x0f) + 0x10));
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}
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return 0;
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}
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int stm32_gpio_get(u32_t *base, int pin)
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{
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struct stm32f4x_gpio *gpio = (struct stm32f4x_gpio *)base;
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return (gpio->idr >> pin) & 0x1;
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}
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int stm32_gpio_enable_int(int port, int pin)
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{
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volatile struct stm32f4x_syscfg *syscfg =
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(struct stm32f4x_syscfg *)SYSCFG_BASE;
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volatile union syscfg_exticr *exticr;
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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struct stm32_pclken pclken = {
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.bus = STM32_CLOCK_BUS_APB2,
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.enr = LL_APB2_GRP1_PERIPH_SYSCFG
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};
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int shift = 0;
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/* Enable SYSCFG clock */
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clock_control_on(clk, (clock_control_subsys_t *) &pclken);
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if (pin <= 3) {
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exticr = &syscfg->exticr1;
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} else if (pin <= 7) {
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exticr = &syscfg->exticr2;
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} else if (pin <= 11) {
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exticr = &syscfg->exticr3;
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} else if (pin <= 15) {
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exticr = &syscfg->exticr4;
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} else {
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return -EINVAL;
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}
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shift = 4 * (pin % 4);
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exticr->val &= ~(0xf << shift);
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exticr->val |= port << shift;
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return 0;
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}
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