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https://github.com/zephyrproject-rtos/zephyr
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50753c1d7d
Add const modifier for hal instances, clock devices pointer, and module base address in npcx drivers to prevent driver functions change them unexpectedly. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
300 lines
8.4 KiB
C
300 lines
8.4 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_gpio
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#include <kernel.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include "gpio_utils.h"
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#include "soc_gpio.h"
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#include "soc_miwu.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(gpio_npcx, LOG_LEVEL_ERR);
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/* GPIO module instances declarations */
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static const struct device *gpio_devs[];
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static int gpio_devs_count;
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/* Driver config */
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struct gpio_npcx_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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/* GPIO controller base address */
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uintptr_t base;
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/* IO port */
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int port;
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/* Size of wui mapping array */
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int wui_size;
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/* Mapping table between gpio bits and wui */
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struct npcx_wui wui_maps[];
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};
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/* Driver data */
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struct gpio_npcx_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct gpio_npcx_config *)(dev)->config)
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#define DRV_DATA(dev) ((struct gpio_npcx_data *)(dev)->data)
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#define HAL_INSTANCE(dev) (struct gpio_reg *)(DRV_CONFIG(dev)->base)
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/* Soc specific GPIO functions */
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const struct device *soc_get_gpio_dev(int port)
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{
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if (port >= gpio_devs_count)
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return NULL;
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return gpio_devs[port];
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}
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/* GPIO api functions */
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static int gpio_npcx_config(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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struct gpio_reg *const inst = HAL_INSTANCE(dev);
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uint32_t mask = BIT(pin);
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/* Don't support simultaneous in/out mode */
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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/* Don't support "open source" mode */
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if (((flags & GPIO_SINGLE_ENDED) != 0) &&
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((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
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return -ENOTSUP;
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}
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/*
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* Configure pin as input, if requested. Output is configured only
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* after setting all other attributes, so as not to create a
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* temporary incorrect logic state 0:input 1:output
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*/
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if ((flags & GPIO_OUTPUT) == 0)
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inst->PDIR &= ~mask;
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/* Select open drain 0:push-pull 1:open-drain */
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if ((flags & GPIO_OPEN_DRAIN) != 0)
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inst->PTYPE |= mask;
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else
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inst->PTYPE &= ~mask;
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/* Select pull-up/down of GPIO 0:pull-up 1:pull-down */
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if ((flags & GPIO_PULL_UP) != 0) {
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inst->PPUD &= ~mask;
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inst->PPULL |= mask;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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inst->PPUD |= mask;
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inst->PPULL |= mask;
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} else {
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/* disable pull down/up */
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inst->PPULL &= ~mask;
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}
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/* Set level 0:low 1:high*/
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0)
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inst->PDOUT |= mask;
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else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0)
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inst->PDOUT &= ~mask;
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/* Configure pin as output, if requested 0:input 1:output */
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if ((flags & GPIO_OUTPUT) != 0)
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inst->PDIR |= mask;
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return 0;
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}
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static int gpio_npcx_port_get_raw(const struct device *dev,
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gpio_port_value_t *value)
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{
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struct gpio_reg *const inst = HAL_INSTANCE(dev);
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/* Get raw bits of GPIO input registers */
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*value = inst->PDIN;
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return 0;
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}
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static int gpio_npcx_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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struct gpio_reg *const inst = HAL_INSTANCE(dev);
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uint8_t out = inst->PDOUT;
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inst->PDOUT = ((out & ~mask) | (value & mask));
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return 0;
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}
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static int gpio_npcx_port_set_bits_raw(const struct device *dev,
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gpio_port_value_t mask)
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{
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struct gpio_reg *const inst = HAL_INSTANCE(dev);
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/* Set raw bits of GPIO output registers */
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inst->PDOUT |= mask;
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return 0;
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}
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static int gpio_npcx_port_clear_bits_raw(const struct device *dev,
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gpio_port_value_t mask)
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{
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struct gpio_reg *const inst = HAL_INSTANCE(dev);
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/* Clear raw bits of GPIO output registers */
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inst->PDOUT &= ~mask;
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return 0;
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}
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static int gpio_npcx_port_toggle_bits(const struct device *dev,
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gpio_port_value_t mask)
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{
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struct gpio_reg *const inst = HAL_INSTANCE(dev);
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/* Toggle raw bits of GPIO output registers */
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inst->PDOUT ^= mask;
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return 0;
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}
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static int gpio_npcx_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_npcx_config *const config = DRV_CONFIG(dev);
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enum miwu_int_mode miwu_mode = NPCX_MIWU_MODE_DISABLED;
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enum miwu_int_trig miwu_trig = NPCX_MIWU_TRIG_NONE;
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if (config->wui_maps[pin].table == NPCX_MIWU_TABLE_NONE) {
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LOG_ERR("Cannot configure GPIO(%x, %d)", config->port, pin);
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return -EINVAL;
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}
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LOG_DBG("pin_int_conf (%d, %d) match (%d, %d, %d)!!!",
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config->port, pin, config->wui_maps[pin].table,
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config->wui_maps[pin].group,
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config->wui_maps[pin].bit);
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/* Determine interrupt is level or edge mode? */
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if (mode == GPIO_INT_MODE_LEVEL)
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miwu_mode = NPCX_MIWU_MODE_LEVEL;
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else if (mode == GPIO_INT_MODE_EDGE)
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miwu_mode = NPCX_MIWU_MODE_EDGE;
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/* Determine trigger mode is low, high or both? */
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if (trig == GPIO_INT_TRIG_LOW)
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miwu_trig = NPCX_MIWU_TRIG_LOW;
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else if (trig == GPIO_INT_TRIG_HIGH)
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miwu_trig = NPCX_MIWU_TRIG_HIGH;
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else if (trig == GPIO_INT_TRIG_BOTH)
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miwu_trig = NPCX_MIWU_TRIG_BOTH;
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/* Call MIWU routine to setup interrupt configuration */
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soc_miwu_interrupt_configure(&config->wui_maps[pin],
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miwu_mode, miwu_trig);
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/* Enable/Disable irq of wake-up input sources */
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if (mode == GPIO_INT_MODE_DISABLED) {
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soc_miwu_irq_disable(&config->wui_maps[pin]);
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} else {
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soc_miwu_irq_enable(&config->wui_maps[pin]);
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}
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return 0;
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}
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static int gpio_npcx_manage_callback(const struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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const struct gpio_npcx_config *const config = DRV_CONFIG(dev);
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struct miwu_io_callback *miwu_cb = (struct miwu_io_callback *)callback;
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int pin = find_lsb_set(callback->pin_mask) - 1;
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/* pin_mask should not be zero */
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if (pin < 0)
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return -EINVAL;
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/* Has the IO pin valid MIWU input source? */
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if (config->wui_maps[pin].table == NPCX_MIWU_TABLE_NONE) {
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LOG_ERR("Cannot manage GPIO(%x, %d) callback!", config->port,
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pin);
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return -EINVAL;
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}
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/* Initialize WUI information in unused bits field */
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soc_miwu_init_gpio_callback(miwu_cb, &config->wui_maps[pin],
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config->port);
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/* Insert or remove a IO callback which being called in MIWU ISRs */
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return soc_miwu_manage_gpio_callback(miwu_cb, set);
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}
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/* GPIO driver registration */
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static const struct gpio_driver_api gpio_npcx_driver = {
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.pin_configure = gpio_npcx_config,
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.port_get_raw = gpio_npcx_port_get_raw,
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.port_set_masked_raw = gpio_npcx_port_set_masked_raw,
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.port_set_bits_raw = gpio_npcx_port_set_bits_raw,
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.port_clear_bits_raw = gpio_npcx_port_clear_bits_raw,
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.port_toggle_bits = gpio_npcx_port_toggle_bits,
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.pin_interrupt_configure = gpio_npcx_pin_interrupt_configure,
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.manage_callback = gpio_npcx_manage_callback,
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};
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int gpio_npcx_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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__ASSERT(DRV_CONFIG(dev)->wui_size == NPCX_GPIO_PORT_PIN_NUM,
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"wui_maps array size must equal to its pin number");
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return 0;
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}
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#define NPCX_GPIO_DEVICE_INIT(inst) \
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static const struct gpio_npcx_config gpio_npcx_cfg_##inst = { \
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.common = { \
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.port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_NGPIOS(NPCX_GPIO_PORT_PIN_NUM),\
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}, \
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.base = DT_INST_REG_ADDR(inst), \
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.port = inst, \
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.wui_size = DT_NPCX_WUI_ITEMS_LEN(inst), \
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.wui_maps = DT_NPCX_WUI_ITEMS_LIST(inst) \
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}; \
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\
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static struct gpio_npcx_data gpio_npcx_data_##inst; \
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\
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DEVICE_AND_API_INIT(gpio_npcx_##inst, \
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DT_INST_LABEL(inst), \
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gpio_npcx_init, \
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&gpio_npcx_data_##inst, \
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&gpio_npcx_cfg_##inst, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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&gpio_npcx_driver);
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DT_INST_FOREACH_STATUS_OKAY(NPCX_GPIO_DEVICE_INIT)
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/* GPIO module instances */
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#define NPCX_GPIO_DEV(inst) DEVICE_GET(gpio_npcx_##inst),
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static const struct device *gpio_devs[] = {
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DT_INST_FOREACH_STATUS_OKAY(NPCX_GPIO_DEV)
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};
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static int gpio_devs_count = ARRAY_SIZE(gpio_devs);
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