zephyr/dts
Jeppe Odgaard d826a69a88 dts: arm: st: stm32h5: fix spi 1-3 clocks
The STM32 SPI driver, `spi_ll_stm32.c`, reads the clock frequency via
`clock_control_get_rate()`. The first `clocks` index is used as subsystem
argument if there is no second index, but this is not the source clock for
SPI 1, 2, and 3.
This causes the prescaler value calculation to be incorrect, resulting in a
frequency potentially above the `spi-max-frequency` value.

Add clock source for SPI instances 1, 2 and 3, that matches the default
clock configuration register reset value, which resolves the issue.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
(cherry picked from commit 40cae2d281)
2024-09-23 06:56:20 -04:00
..
arc/synopsys
arm dts: arm: st: stm32h5: fix spi 1-3 clocks 2024-09-23 06:56:20 -04:00
arm64
bindings drivers: sdhc: imx_usdhc: assume card is present if no detection method 2024-08-31 06:51:21 -04:00
common
nios2/intel
posix
riscv
sparc/gaisler
x86/intel
xtensa
binding-template.yaml
Kconfig