Nathaniel Graff 596e44d244 soc/riscv32-fe310: Enable DTS gen for SPI ... Add the SPI bus DTS generation to the FE310 and the SiFive Freedom SoC. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>		2019-02-06 09:00:00 -06:00
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arc
arm	dts: Fix varying baudrate settings for CAN	2019-02-05 18:47:47 -06:00
bindings	drivers/spi: Generate clock-frequency for SPI bus	2019-02-06 09:00:00 -06:00
common
nios2
riscv32	soc/riscv32-fe310: Enable DTS gen for SPI	2019-02-06 09:00:00 -06:00
x86	gpio: intel_apl: rework driver for pin_mask callback	2019-02-06 07:18:15 -05:00
xtensa
Kconfig