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The fractional part of the divider value is a 4 bit value. Setting it to
255 leads to an overflow in pwm_rpi_get_clkdiv(). This has resulted in a
slight deviation from the reported timing, which is btw. printed in nsec.
Fixes:
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.. | ||
esp32.conf | ||
esp32.overlay | ||
esp32c3_devkitm.conf | ||
esp32c3_devkitm.overlay | ||
esp32s2_saola.conf | ||
esp32s2_saola.overlay | ||
nucleo_f091rc.overlay | ||
nucleo_l4r5zi.overlay | ||
nucleo_l073rz.overlay | ||
nucleo_l476rg.overlay | ||
rcar_h3ulcb_cr7.overlay | ||
rpi_pico.overlay |