mirror of
https://github.com/zephyrproject-rtos/zephyr
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726d4dc437
After activation of cube based driver support on L4 and F3 series, this commits performs the clean up of F3 and L4 relative code to native clock control drivers. Indirectly, it makes pwm driver supported de facto on F3 series Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
314 lines
7.8 KiB
C
314 lines
7.8 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <board.h>
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#include <pwm.h>
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#include <device.h>
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#include <kernel.h>
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#include <init.h>
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#include <clock_control/stm32_clock_control.h>
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#include "pwm_stm32.h"
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct pwm_stm32_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct pwm_stm32_data * const)(dev)->driver_data)
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#define PWM_STRUCT(dev) \
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((TIM_TypeDef *)(DEV_CFG(dev))->pwm_base)
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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#define CLOCK_SUBSYS_TIM1 STM32F10X_CLOCK_SUBSYS_TIM1
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#define CLOCK_SUBSYS_TIM2 STM32F10X_CLOCK_SUBSYS_TIM2
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#endif
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#define CHANNEL_LENGTH 4
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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static uint32_t __get_tim_clk(uint32_t bus_clk,
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clock_control_subsys_t *sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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uint32_t tim_clk, apb_psc;
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32_APB1_PRESCALER;
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} else {
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apb_psc = CONFIG_CLOCK_STM32_APB2_PRESCALER;
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}
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if (apb_psc == RCC_HCLK_DIV1) {
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tim_clk = bus_clk;
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} else {
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tim_clk = 2 * bus_clk;
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}
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return tim_clk;
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}
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#else
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#ifdef CONFIG_SOC_SERIES_STM32F4X
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static uint32_t __get_tim_clk(uint32_t bus_clk,
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clock_control_subsys_t *sub_system)
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{
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struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
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uint32_t tim_clk, apb_psc;
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if (pclken->bus == STM32F4X_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32F4X_APB1_PRESCALER;
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} else {
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apb_psc = CONFIG_CLOCK_STM32F4X_APB2_PRESCALER;
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}
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if (apb_psc == RCC_HCLK_DIV1) {
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tim_clk = bus_clk;
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} else {
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tim_clk = 2 * bus_clk;
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}
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return tim_clk;
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}
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#else
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static uint32_t __get_tim_clk(uint32_t bus_clk,
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clock_control_subsys_t sub_system)
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{
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uint32_t tim_clk, apb_psc;
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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if (subsys > STM32F10X_CLOCK_APB2_BASE) {
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apb_psc = CONFIG_CLOCK_STM32F10X_APB2_PRESCALER;
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} else {
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apb_psc = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
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}
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if (apb_psc == RCC_HCLK_DIV1) {
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tim_clk = bus_clk;
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} else {
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tim_clk = 2 * bus_clk;
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}
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return tim_clk;
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}
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#endif /* CONFIG_SOC_SERIES_STM32F4X */
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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/*
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* Set the period and pulse width for a PWM pin.
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*
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* Parameters
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* dev: Pointer to PWM device structure
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* pwm: PWM channel to set
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* period_cycles: Period (in timer count)
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* pulse_cycles: Pulse width (in timer count).
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*
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* return 0, or negative errno code
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*/
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static int pwm_stm32_pin_set(struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles)
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{
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struct pwm_stm32_data *data = DEV_DATA(dev);
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TIM_HandleTypeDef *TimerHandle = &data->hpwm;
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TIM_OC_InitTypeDef sConfig;
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uint32_t channel;
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bool counter_32b;
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if (period_cycles == 0 || pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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/* configure channel */
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channel = (pwm - 1)*CHANNEL_LENGTH;
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if (!IS_TIM_INSTANCE(PWM_STRUCT(dev)) ||
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!IS_TIM_CHANNELS(channel)) {
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return -ENOTSUP;
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}
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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/* FIXME: IS_TIM_32B_COUNTER_INSTANCE not available on
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* SMT32F1 Cube HAL since all timer counters are 16 bits
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*/
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counter_32b = 0;
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#else
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counter_32b = IS_TIM_32B_COUNTER_INSTANCE(PWM_STRUCT(dev));
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#endif
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if (!counter_32b && (period_cycles > 0xFFFF)) {
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/* 16 bits counter does not support requested period
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* You might want to adapt PWM output clock to adjust
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* cycle durations to fit requested period into 16 bits
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* counter
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*/
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return -ENOTSUP;
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}
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/* Configure Timer IP */
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TimerHandle->Instance = PWM_STRUCT(dev);
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TimerHandle->Init.Prescaler = data->pwm_prescaler;
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TimerHandle->Init.ClockDivision = 0;
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TimerHandle->Init.CounterMode = TIM_COUNTERMODE_UP;
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TimerHandle->Init.RepetitionCounter = 0;
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/* Set period value */
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TimerHandle->Init.Period = period_cycles;
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HAL_TIM_PWM_Init(TimerHandle);
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/* Configure PWM channel */
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sConfig.OCMode = TIM_OCMODE_PWM1;
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sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
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sConfig.OCFastMode = TIM_OCFAST_DISABLE;
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sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
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sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
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sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
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/* Set the pulse value */
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sConfig.Pulse = pulse_cycles;
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HAL_TIM_PWM_ConfigChannel(TimerHandle, &sConfig, channel);
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return HAL_TIM_PWM_Start(TimerHandle, channel);
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}
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/*
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* Get the clock rate (cycles per second) for a PWM pin.
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*
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* Parameters
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* dev: Pointer to PWM device structure
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* pwm: PWM port number
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* cycles: Pointer to the memory to store clock rate (cycles per second)
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*
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* return 0, or negative errno code
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*/
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static int pwm_stm32_get_cycles_per_sec(struct device *dev, uint32_t pwm,
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uint64_t *cycles)
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{
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const struct pwm_stm32_config *cfg = DEV_CFG(dev);
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struct pwm_stm32_data *data = DEV_DATA(dev);
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uint32_t bus_clk, tim_clk;
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if (cycles == NULL) {
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return -EINVAL;
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}
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/* Timer clock depends on APB prescaler */
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#if defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&cfg->pclken, &bus_clk);
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tim_clk = __get_tim_clk(bus_clk,
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(clock_control_subsys_t *)&cfg->pclken);
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#else
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clock_control_get_rate(data->clock, cfg->clock_subsys, &bus_clk);
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tim_clk = __get_tim_clk(bus_clk, cfg->clock_subsys);
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#endif
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*cycles = (uint64_t)(tim_clk / (data->pwm_prescaler + 1));
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return 0;
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}
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static const struct pwm_driver_api pwm_stm32_drv_api_funcs = {
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.pin_set = pwm_stm32_pin_set,
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.get_cycles_per_sec = pwm_stm32_get_cycles_per_sec,
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};
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static inline void __pwm_stm32_get_clock(struct device *dev)
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{
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struct pwm_stm32_data *data = DEV_DATA(dev);
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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data->clock = clk;
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}
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static int pwm_stm32_init(struct device *dev)
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{
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const struct pwm_stm32_config *config = DEV_CFG(dev);
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struct pwm_stm32_data *data = DEV_DATA(dev);
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__pwm_stm32_get_clock(dev);
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/* enable clock */
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#if defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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clock_control_on(data->clock,
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(clock_control_subsys_t *)&config->pclken);
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#else
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clock_control_on(data->clock, config->clock_subsys);
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#endif
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return 0;
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}
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#ifdef CONFIG_PWM_STM32_1
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static struct pwm_stm32_data pwm_stm32_dev_data_1 = {
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/* Default case */
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.pwm_prescaler = 10000,
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};
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static const struct pwm_stm32_config pwm_stm32_dev_cfg_1 = {
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.pwm_base = TIM1_BASE,
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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.pclken = { .bus = STM32_CLOCK_BUS_APB2,
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.enr = LL_APB2_GRP1_PERIPH_TIM1 },
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#else
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#ifdef CONFIG_SOC_SERIES_STM32F4X
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.pclken = { .bus = STM32F4X_CLOCK_BUS_APB2,
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.enr = STM32F4X_CLOCK_ENABLE_TIM1 },
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#else
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.clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM1),
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#endif /* CONFIG_SOC_SERIES_STM32F4X */
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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};
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DEVICE_AND_API_INIT(pwm_stm32_1, CONFIG_PWM_STM32_1_DEV_NAME,
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pwm_stm32_init,
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&pwm_stm32_dev_data_1, &pwm_stm32_dev_cfg_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pwm_stm32_drv_api_funcs);
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#endif /* CONFIG_PWM_STM32_1 */
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#ifdef CONFIG_PWM_STM32_2
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static struct pwm_stm32_data pwm_stm32_dev_data_2 = {
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/* Default case */
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.pwm_prescaler = 0,
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};
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static const struct pwm_stm32_config pwm_stm32_dev_cfg_2 = {
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.pwm_base = TIM2_BASE,
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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.pclken = { .bus = STM32_CLOCK_BUS_APB1,
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.enr = LL_APB1_GRP1_PERIPH_TIM2 },
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#else
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#ifdef CONFIG_SOC_SERIES_STM32F4X
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.pclken = { .bus = STM32F4X_CLOCK_BUS_APB1,
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.enr = STM32F4X_CLOCK_ENABLE_TIM2 },
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#else
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.clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM2),
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#endif /* CONFIG_SOC_SERIES_STM32F4X */
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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};
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DEVICE_AND_API_INIT(pwm_stm32_2, CONFIG_PWM_STM32_2_DEV_NAME,
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pwm_stm32_init,
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&pwm_stm32_dev_data_2, &pwm_stm32_dev_cfg_2,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pwm_stm32_drv_api_funcs);
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#endif /* CONFIG_PWM_STM32_2 */
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