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https://github.com/zephyrproject-rtos/zephyr
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50753c1d7d
Add const modifier for hal instances, clock devices pointer, and module base address in npcx drivers to prevent driver functions change them unexpectedly. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/pinmux.h>
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#include <kernel.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pimux_npcx, LOG_LEVEL_ERR);
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/* Driver config */
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struct npcx_pinctrl_config {
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/* scfg device base address */
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uintptr_t base;
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};
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/* Default io list which default functionality are not IOs */
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#define DT_DRV_COMPAT nuvoton_npcx_pinctrl_def
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static const struct npcx_alt def_alts[] = DT_NPCX_ALT_ITEMS_LIST(0);
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static const struct npcx_pinctrl_config npcx_pinctrl_cfg = {
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.base = DT_REG_ADDR(DT_NODELABEL(scfg)),
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) \
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((const struct npcx_pinctrl_config *)(dev)->config)
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#define HAL_INSTANCE(dev) \
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(struct scfg_reg *)(DRV_CONFIG(dev)->base)
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/* Pin-control local functions */
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static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func)
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{
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const uint32_t scfg_base = npcx_pinctrl_cfg.base;
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uint8_t alt_mask = BIT(alt->bit);
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/*
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* alt_fun == 0 means select GPIO, otherwise Alternate Func.
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* inverted == 0:
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* Set devalt bit to select Alternate Func.
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* inverted == 1:
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* Clear devalt bit to select Alternate Func.
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*/
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if (!!alt_func != !!alt->inverted)
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NPCX_DEVALT(scfg_base, alt->group) |= alt_mask;
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else
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NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask;
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}
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/* Soc specific pin-control functions */
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void soc_pinctrl_mux_configure(const struct npcx_alt *alts_list,
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uint8_t alts_size, int altfunc)
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{
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int i;
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for (i = 0; i < alts_size; i++, alts_list++) {
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npcx_pinctrl_alt_sel(alts_list, altfunc);
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}
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}
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/* Pin-control driver registration */
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static int npcx_pinctrl_init(const struct device *dev)
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{
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struct scfg_reg *const inst = HAL_INSTANCE(dev);
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#if defined(CONFIG_SOC_SERIES_NPCX7)
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/*
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* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
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* for more information. It will be fixed in next chip.
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*/
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inst->DEVCNT |= BIT(7);
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#endif
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/* Change all pads whose default functionality isn't IO to GPIO */
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soc_pinctrl_mux_configure(def_alts, ARRAY_SIZE(def_alts), 0);
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return 0;
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}
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DEVICE_AND_API_INIT(npcx_pinctrl,
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DT_LABEL(DT_NODELABEL(scfg)),
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&npcx_pinctrl_init,
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NULL, &npcx_pinctrl_cfg,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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NULL);
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