mirror of
https://github.com/zephyrproject-rtos/zephyr
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984bfae831
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and .yaml files. Will avoid failures with the new CI test in https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only checks changed files. Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst to get rid of the trailing blank line there. It was probably misplaced. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
68 lines
1.4 KiB
C
68 lines
1.4 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_API_H_
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#define ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_API_H_
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#include <xtensa/hal.h>
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#include "xtensa_rtos.h"
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#include "xtensa_context.h"
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/*
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* Call this function to enable the specified interrupts.
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*
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* mask - Bit mask of interrupts to be enabled.
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*/
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static inline void z_xt_ints_on(unsigned int mask)
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{
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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val |= mask;
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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/*
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* Call this function to disable the specified interrupts.
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*
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* mask - Bit mask of interrupts to be disabled.
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*/
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static inline void z_xt_ints_off(unsigned int mask)
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{
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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val &= ~mask;
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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/*
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* Call this function to set the specified (s/w) interrupt.
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*/
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static inline void z_xt_set_intset(unsigned int arg)
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{
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#if XCHAL_HAVE_INTERRUPTS
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__asm__ volatile("wsr.intset %0; rsync" : : "r"(arg));
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#else
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ARG_UNUSED(arg);
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#endif
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}
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/* Call this function to clear the specified (s/w or edge-triggered)
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* interrupt.
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*/
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static inline void _xt_set_intclear(unsigned int arg)
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{
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#if XCHAL_HAVE_INTERRUPTS
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__asm__ volatile("wsr.intclear %0; rsync" : : "r"(arg));
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#else
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ARG_UNUSED(arg);
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#endif
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}
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#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_API_H_ */
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