Jaron Kelleher d63651dd01 riscv machine timer: Timer functions on long running platforms ... When debugging on a long running platform, the MCU may get reset by the debugger with an ndmreset toggle. Since there is no requirement that this resets anything in particular on the platform, the CLINT registers may not get reset. When this occurs with an mtime register value that is larger than 32 bits the riscv machine timer will continuously interrupt the system when the mtime register exceeds 32 bits in value. This is because the last_count value is used to update the mtimecmp register, and its value is initialized to zero. Its first update is with a 32-bit value, which loses information when the mtime register exceeds 32 bits. The proposed solution is to set the last_count value to the current value in the mtime register when the timer is initialized. Since the timer is fired at intervals that are less than 32 bits in value, the next update of last_count will remain valid, and the system will function as expected. Signed-off-by: Jaron Kelleher <jkelleher@fb.com>		2020-03-04 23:08:49 +02:00
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altera_avalon_timer_hal.c
apic_timer.c
arcv2_timer0.c
arm_arch_timer.c	drivers: timer: Add per-core ARM architected timer	2020-02-01 08:08:43 -05:00
cc13x2_cc26x2_rtc_timer.c
CMakeLists.txt	drivers: timer: Add per-core ARM architected timer	2020-02-01 08:08:43 -05:00
cortex_m_systick.c
hpet.c
Kconfig	drivers: timer: Add per-core ARM architected timer	2020-02-01 08:08:43 -05:00
Kconfig.stm32_lptim
legacy_api.h
litex_timer.c
loapic_timer.c	drivers: loapic_timer: simplify TSC read	2020-02-06 23:07:37 -05:00
mchp_xec_rtos_timer.c
native_posix_timer.c	native_posix: timer: Improve arch_busy_wait() doc	2020-02-07 11:48:41 +01:00
nrf_rtc_timer.c
riscv_machine_timer.c	riscv machine timer: Timer functions on long running platforms	2020-03-04 23:08:49 +02:00
rv32m1_lptmr_timer.c
sam0_rtc_timer.c
stm32_lptim_timer.c
sys_clock_init.c
xlnx_psttc_timer.c
xtensa_sys_timer.c