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a51f88638e
When exiting from tickless idle uppon an external IRQ, the TICK timer is set to fire at next TICK boundary. The current algorithm can lead to a point that timer0_count register is higher than the timer0_limit register. In this situation the next TICK will fire after the counter has wrapped and performed another cycle (~133 seconds). This condition appears when the counter reaches the limit after the Interrupt Pending flag is checked. At this point the counter is automatically wrapped to 0, but is set just next to the limit to fire at next TICK boundary by SW. At exit of the _timer_idle_exit function, the timer handler is called, and sets the limit to 1 TICK. At this point the situation is: - limit register == 1 TICK - count register is just below the old limit register and higher than 1 TICK To fix this issue, at _timer_idle_exit, the limit register is always set to 1 TICK and the count register set such as the next TICK fires on time. Change-Id: Ifa002809d426aa04109592e53d2b02a224f51101 Signed-off-by: Simon Desfarges <simon.desfarges@intel.com> |
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| .. | ||
| arcv2_timer0.c | ||
| cortex_m_systick_gdb.S | ||
| cortex_m_systick.c | ||
| hpet.c | ||
| Kconfig | ||
| loapic_timer.c | ||
| Makefile | ||
| sys_clock_init.c | ||